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ADS7881 timing question

Timothy Starr
Expert 2445 points
Other Parts Discussed in Thread: ADS7881, AM3703

Hello-

Regarding the ADS7881 12b SAR. My cusotmer is trying to use it between a contact imagesensor and a AM3703 based SoM. His question:

"Is it safe to assume that the voltage that gets converted to digital is the actual voltage present at the analog input the instant /CONVST transitions from low to high (at either 50% or 90% threshold) ?

The reason I am trying to get a better understanding is because we are going to need to pick a time where our analog data is stable.

I have included my own timing diagram and also included an actual screenshot. See attachment.

 

The 3rd waveform is representative of output from contact image sensor.  I would like to sample the analog signal at input to ADC at time (1).

 

 

At time (2) we can initiate ADC conversion and switch to the next video pixel.

I am also thinking it would be best to read 12 bit data at time (1) so we would send this signal to the AM3705 CAM_PCLK input."

Thanks and best regards,

Tim Starr on behalf of JY

 

ads7881 timing.docx
  • 0
    TI__Mastermind 44620 points

    Hi Timothy,

    /CONVST Clarification:
    First I want to clarify the /CONVST logic for the customer. It was stated backwards in their question but shown correct in their timing diagram:

    • The rising edge of /CONVST starts the sampling phase
    • The falling edge of /CONVST ends the sampling phase and begins conversion phase

    The analog voltage that gets converted to a digital signal is the voltage that the internal sampling capacitor is charged up to when the ADC goes into the conversion phase. This value MAY or MAY NOT be exactly the same as the voltage present at the analog input. To have these values be the same and convert the correct value:

    • either more sampling time must be given to the part to ensure that the internal sampling capacitor gets fully charged up (to within 1/2 LSB of the analog input)
    • or the use of an external op-amp driver/buffer circuit is used to help charge up the internal sampling capacitor quicker
    • or both to reduce the bandwidth requirements of the drive circuitry.

     

    Timing Diagram
    Regarding the timing diagram, at point 1 the ADC begins sampling the input, and at point 2 the ADC stops sampling and begins converting. The converted digital voltage will be the value the internal sampling capacitor was able to charge up to from the time period between point 1 and 2. Point 3 shows the point at which the converstion completes.
    Data reading can be done any time after point 3 but it must finish at least 25 ns (quiet sampling time "t1" in timing requirements) before the next conversion begins.

    Suggestion: After point 3 it looks like there is a long delay before the next point is sampled and converted. For a more accurate conversion result (or to ensure that the sampling capacitor has more time to charge up to the applied analog input voltage) start sampling earlier by setting /CONVST HIGH shortly after BUSY goes LOW (even though the analog input voltage for the next conversion is still settling). You may need to split CIS CLK and /CONVST into two different signals to accomplish this. If that is not a possibility you may be able to use the same signal for both but invert the signal for /CONVST. This should be fairly straight-forward to implement, especially if /CS is held low for the entire operation of the ADS7881.

    Be sure to check the timing requirements for min & max delay and holding times on pages 5, 8, & 9 of the ADS7881 Datasheet for proper operation.

    Best Regards,
    Chris