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DAC38J84EVM: How to enable DAC output with fixed delay

Spencer Chen
Prodigy 20 points
Part Number: DAC38J84EVM
Other Parts Discussed in Thread: LMK04828, DAC38J84

Hi,

I am use a sys_sync signal to enable the DAC output. After the rising edge of sys_sync signal reach to the SYNC of LMK04828, there are outputs on the SDCLKout*.

I can capture the SDCLKout*, but the delay between sys_sync and SDCLKout*. 

my system setup details are shown below:

1. I have 100MHz input on the input1.

2. the DAC data rate is 400MSPS, I am using 2 as the interpolation.

Can you give me some suggestions about how to configure the LMK04828 and DAC38j84? Thanks!

  • 0
    TI__Guru 66074 points

    Hi,

    You may use the DAC38J84 GUI to generate the configuration of both the LMK04828 and DAC38j84

    https://www.ti.com/lit/zip/slac644

    You will need to also input the system parameter like the number of JESD204B lanes in your setup.

    -Kang

  • 0 in reply to Kang Hsia
    Prodigy 20 points

    Hi Kang,

    Thanks for your reply!

    Yes, I use the GUI to generate the configuration. But the evaluation board uses SPI to trigger the sync.

    I am trying to use the sync pin to trigger the sysref. The results show that the delay between the SYNC and sysref is not constant. Do you have any idea about this issue? Thanks!

    Spencer Chen

  • 0 in reply to Spencer Chen
    TI__Guru 66074 points

    Hello Spencer,

    I do not believe the LMK04828 can support consistent delay from using external SYNC pin. The uncertainty comes from what will be the clock to latch in the SYNC and the consistency of the setup/hold time of the clock. Once the clock used to latch the SYNC, the PLL loop may change behavior after synchronization, and changes the perspective of the delay again. Above is based on my user's experience and prior conversation with the clocking team.

    Please do post your questions on the clocking forum so the clocking experts can better comment on your questions. Thanks. 

    -kang