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ADC32RF45EVM: SFDR issue limited by HD2

Part Number: ADC32RF45EVM

Hello,

Our ADC32RF45EVM board is connected to FPGA mother board TSW14J56 (Rev E.).

With have the following configurations :

  • fs=3GHz (external clock provided with SMA100A : +15dBm and 3GHz filter)
  • This clock is connected to J5 and J7
  • fin is filtered (SMA100A RF generator)
  • Pin adjusted to -2dBFS
  • 2 Keysight power supplies are used with current limitation above 5A

The following SFDR are measured :

  • 100MHz : 63dBc
  • 900MHz : 61dBc
  • 1850MHz : 56dBc
  • 2100MHz : 50dBc
  • 2600MHz : 36 dBc
  • 3500MHz : 45dBc (-3dBFS & G=-2dB)

You can see that we are far away from figures provided in the datasheet.

We have 2 ADC32RF45EVM board, and they have both bad results regarding SFDR.

The HD2 is the limiting parameter.

We can provide FFT screenshot, files etc...

Results a slightly different from a channel to another but remain not in line with datasheet figures.

ADC32RF45EVM boards are :

  • RF45-341
  • RF45-333

Similar results are obtained when internal clock is used (LMX PLL).

Could you please give us your feeling about that issue ?

Best regards.

  • Hi Laurent,

    Can you please share the filter that is being used on the analog input?

    Also, please share some of the FFT plot that were captured. This will help us debug this issue for you.

    Regards,

    Rob

  • Hi Rob,

    Filters which have been used are very good filters from EWT.

    I have checked harmonics with spectrum analyzer at filters output and harmonic levels are far away from what we can see in your analysis software (HDSC PRO).

    Please find a FFT plot (fs=3GHz / fin=2600.418091MHz / Pin =-2dBFS). Hope it will help you to find the issue.

    Laurent

  • Hi Rob,

    Filters are from EWT and are very good. I have checked harmonics at filters output with spectrum anayzer and levels are far away from what we see in HSDC Pro.

    Please find below a measured FFT (fs=3GHz / fin=2600.418091MHz / -2dBFS). Hope it can help.

    Best regards.

    Laurent

  • Hi Laurent,

    I will need to find a board and check it out on the lab bench.

    In the meantime, are there any specific register spi writes that are being written in your setup? If so, can you please forward the list to me?

    Do you see any damage to the EVM on the back to back balun frontend?

    Regards,

    Rob

  • Hi Rob,

    There are no specific registers we would have writtent into.

    As mentionned above, we have two EVM boards and both of them have the same behaviour.

    ADC32RF45EVM boards are :

    • RF45-341
    • RF45-333

    I have had the same idea you mentionned, and I have already checked the boards without seeing any damage, especially the baluns.

    Laurent

  • please find the setup below :

    For your information, problem is the same with internal clock

    Laurent

  • Hi Laurent,

    Are you selecting the right Nyquist zone (see below marked Nyquist zone selection in GUI)

    For 2.6GHz input with 3GSPS sampling rate, you should select 2nd Nyquist.

    Can you please share time domain plot of HSDC Pro capture window? 

    Regards,

    Vijay

  • Hi Vijay,

    As we have swept several frequencies (as mentioned in my initial post) I have put the screenshot relative to the lower frequency.

    You are right, we have selected the 2nd Nyquiest zone for 2.6GHz.

    I have tried both (1st and 2nd @2.6GHz), and there no significant difference.

    Laurent

  • Hi Laurent,

    Thank you for checking, we are ordering an EVM ourselves out of stock to check and see if we can better find the issue here.

    Please give us a few days to receive the EVM, setup and check. We will report back out findings.

    Thank you for your patience.

    Regards,

    Rob

  • Hi Laurent,

    We just received the EVM today. I will work on this tomorrow and hopefully get you some results.

    Regards,

    Rob

  • Hi Rob,

    Thank you for the information. I am eager to see your results.

    Best rergards

    Laurent

  • Hi Laurent,

    On the new EVM we have, we are seeing the same HD2/3 limitation in SFDR as you have reported.

    We believe there is an old configuration file that is out dated and not configuring the ADC properly.

    We are working with the design team to get this updated.

    I will keep you posted.

    Thank you for your patience!

    Regards,

    Rob

  • Hi Laurent,

    Just a quick update. We are still working thru this. Attached is an FFT plot of the EVM at a lower input frequency in 1st Nyquist. See attached. This is in line with the datasheet performance.

    We believe there is a different input network & balun used to characterize the 2nd Nyquist performance. We are trying some experiments now and have improved the HD2 performance, but we are not quite there yet where we meet the DS performance.

    I will try to update you more tomorrow. Thank you for your patience.

    Regards,

    Rob

  • Hi Rob,

    Thank you for the update and the shared results.

    Even in the first Nyquist zone we are not completly in line with the datasheet. For example, @900MHz we have measured 61dBc for the SFDR while the typical value in the DS is 67dBc... However, results in the 1st Nyquist zone are clearly better compared to the 2nd zone where we have huge differences.

    It seems you have finally given up the configuration file lead and you now suspect the baluns performances.

    Did you find something related to that ?

    Best regards.

    Laurent

  • Hi Laurent,

    We have finally been able to get -55dB on the HD2 performance in the second Nyquist zone.

    We are putting together a configuration file for you and the baluns will need to be changed out to the following part for both baluns.

    Minicircuits: TC1-1-43X+

    If you would like us to modify your EVMs, please let me know.

    Regards,

    Rob

  • Hi Rob,

    Today, on the EVM board, there are MACOM baluns ETC1-1-13. If I well unsterstand it is necessary to change all these baluns with Mini Circuits balun TC1-1-43X+. I mean baluns for clock signal and input signal.

    Do you know why TI provided theses EVM board with baluns which does not allow customers to reach TI datasheet figures ?

    It seems we won't able to work below 650MHz with these new baluns...

    Could you tell us which key parameter of the balun permit to improve this SFDR ? phase unbalance ?

    Last point : the SFDR datasheet figures are better thant the -55dBc you finally reached. For example, i can read -66 & -65dBc for respectively 1850MHz and 2100MHz as typical values. Do you have any explanation about that ?

    Best regards.

    Laurent

  • Hi Laurent,

    If in your application the plan is to use the 2nd Nyquist zone, then yes something like the TC1-1-43X+ will need to be used only on the analog inputs, not the clock. Yes, this is due to phase imbalance.

    I am not sure of the history on why the EVM was only outfitted with other balun, ETC1-1-13. These would be more suited for 1st Nyquist.

    Attached is the new configuration file, this should be used only when operating in the second Nyquist. To program this file, first setup the EVM in DDC bypass mode through GUI. Then go to low level view and load the attached p1 and p2 configs respectively. I apologize for the delay.

    With the new configs and baluns updated to TC1-1-43X+, we see SFDR at 2.6GHz is in-line with data sheet specification. 

    Regards,

    Vijay

    WebConfigRF45_DDC_Bypass_ny2_p1.cfgWebConfigRF45_DDC_Bypass_ny2_p2.cfg

  • Hi Vijay,

    Thank you for your message and the configuration files. We will try them.

    Do you know where the major difference comes from ? Config files or balun ?  or 50/50 ?

    Best regards.

    Laurent

  • Hi Laurent,

    Hd2 is dependent on input phase imbalance so major contribution from the balun configuration. 

    Hd3 improves to datasheet specified values when using the latest config. 

    regards,

    Vijay

  • Hi Vijay,

    Thank you for the detail.

    Best regards.

    Laurent