Hello,
Our ADC32RF45EVM board is connected to FPGA mother board TSW14J56 (Rev E.).
With have the following configurations :
- fs=3GHz (external clock provided with SMA100A : +15dBm and 3GHz filter)
- This clock is connected to J5 and J7
- fin is filtered (SMA100A RF generator)
- Pin adjusted to -2dBFS
- 2 Keysight power supplies are used with current limitation above 5A
The following SFDR are measured :
- 100MHz : 63dBc
- 900MHz : 61dBc
- 1850MHz : 56dBc
- 2100MHz : 50dBc
- 2600MHz : 36 dBc
- 3500MHz : 45dBc (-3dBFS & G=-2dB)
You can see that we are far away from figures provided in the datasheet.
We have 2 ADC32RF45EVM board, and they have both bad results regarding SFDR.
The HD2 is the limiting parameter.
We can provide FFT screenshot, files etc...
Results a slightly different from a channel to another but remain not in line with datasheet figures.
ADC32RF45EVM boards are :
- RF45-341
- RF45-333
Similar results are obtained when internal clock is used (LMX PLL).
Could you please give us your feeling about that issue ?
Best regards.