I would like to know about the frequency response characteristics.
If SCLK is set to 12MHz and the voltage is output as a sine wave up to full scale (LSB to MSB), how much band can be output? The communication mode is SPI.
I want to output a full-scale sine wave at 12kHz, so if you know the attenuation factor and phase lag at that frequency, that information is fine.
Hello,
The 12kHz sine wave will depend on the update rate of the DAC and how many data points you would like per period. In this case the settling time of the output buffer is going to be the limiting factor of the update rate. The DAC has longer settling time when coming out of the supply rail (VDD or ground) so you may not want to do a true full-scale wave. Instead you could use fullscale to 1/32th scale, and if your full scale output is at VDD then also stay a few codes below full scale to avoid the longer settling time.
The settling time in the datasheet is given as 5us meaning that the DAC update rate is 200kHz. So you could fit a total of 16 data points and still output a 12kHz sine wave. You would need to update the DAC every 180kHz which can be done with a 12MHz SCLK. Each SPI write to the DAC output register takes 24 bits.
This 5us settling time is given to ±2LSB (shown by the black curve below). You can see that the red curve settles to within a few percent of the final value faster than 5us. If this is ok for your application then you could probably add a few more points to the waveform and still meet 12kHz.
Best,
Katlynne Jones
