I am following the pseudo code given in the data sheet for programming the FPGA.
1.First i am giving reset command and waiting for 4096 tclk(sclk =3Mhz)
2.i am reading the status register which is giving RDY bit 1 which says adc not ready for communication.
how much time i need to wait for this bit to be 0 as i need to clear the POR flag (FL_POR) in status register by writing 0.(as per the pseudo code).
When i have to send RDATA command,,i mean as per the data sheet i understood that after start command drdy becomes high(7 sclk falling edge) ,unless i send stop command DRDY will it become low??? or DRDY is independent of stop command.
can i follow the following pattern for reading data after programming the registers through Din:
1.send start command
2.check for drdy low
3.send rdata command.
4.read the data
5.send stop command
6.again start from 2
if there is any wrong in the reading pattern request u to correct us