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DAC37J84: SERDES PLLs doesn't lock

Part Number: DAC37J84
Other Parts Discussed in Thread: DAC37J82

I have dac37j84 on a custom board, and its SERDES PLLs doesn't want to lock.
I understood it by reading 0x6C register - it's value is 0x000F (yes, I've tried to reset it to 0x0000).
Reference to SERDES PLL is DACCLK, which is 390.625 M.
SERDES divider is 1.
SERDES multiplier is 5, SERDES clock is 390.625 M * 5 = 1953.125 M.
DAC is operating at full rate, so linerate = SERDES clock * 4 = 7812.5 M.
L = 3 (4 JESD lanes), lanes 0-3 are enabled (yes, I've tried to enable all lanes).
M = 1 (2 streams per frame)
F = 0 (1 octet in the frame)
K = 19 (20 frames in multiframe)
SYSREF is 39.0625 M, but it is disabled, according to Initialization Set Up (I also tried with enabled SYSREF).
I've also tried to reset DAC through RESETB pin - registers became default, then I programmed it again - that didn't help.

PLEASE help me, what should I do?

Here is my full config:


  • Art,

    Your SYSREF is to fast. The max rate you can use for SYSREF is 19.53125MHz.

    Max SYSREF = data rate / (K *N) where N is any whole integer. I am assuming you are not using any interpolation and your data rate is 390.625MSPS.

    With a DAC clock of 390.625MHz and LMF = 421, this would equate to a serdes rate of 3906.25Mbps. Not sure where you got 7812.5M.

    I have my setup running with your parameters. Attached is the register settings used by the DAC.

    Why are you using a DAC37J84 with only two of the outputs? We offer a 2 channel version of this same device, the DAC37J82. 




  • Jim, thanks for your answer.

    Yes, I'm not using interpolation and data rate = DAC clock.

    Yes, my SYSREF is too fast, I should change it. But is it used by SERDES PLLs?

    We have LMF = 421 configuration for our Xilinx FGPA, so we want to use it to check if we are doing right. Then we are going to switch to LMF = 442.

    I have another question: should I send commas (JESD K28.5 symbols) to DAC to lock its SERDES PLLs?

    Thanks for your config, I'll try it.

  • Art,

    SYSREF is critical for bringing up the link but I do not think it is used with locking the serdes PLL. If the serdes PLL does not lock, this is usually a frequency mismatch between the transmitter and receiver.

    I do think the K28.5 symbols are required because the serdes needs to have data that is switching so a clock can be derived from it. 

    If interested, TI now provides free JESD204B IP that works on all Xilinx devices. You can request this IP by going to the following link:



  • Jim,
    Thanks for your answer.

    I've tried your config.
    It took me a while to understand, that 4-wire SPI is disabled in this config.

    I still get 0x000F at 0x6C register; looks like I should change linerate in my FPGA bitstream.

    Could you, please, share linerate, that you use? Is it 3906.25 M?

  • Art,

    Yes, the lane rate I used is 3906.25Mbps.


  • Finally I succeeded in locking SERDES PLL with your config, thanks again. The problem was in high level on DAC SLEEP.