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DAC37J84: PLL does not lock

Part Number: DAC37J84

Hi Team,

Posting for our customer working on a DAC37J84 custom board, currently experiencing an issue where its SerDes PLLs doest want to lock.

I understood it by reading 0x6C register - it's value is 0x000F (yes, I've tried to reset it to 0x0000).
Reference to SERDES PLL is DACCLK, which is 390.625 M.
SERDES divider is 1.
SERDES multiplier is 5, SERDES clock is 390.625 M * 5 = 1953.125 M.
DAC is operating at full rate, so linerate = SERDES clock * 4 = 7812.5 M.
L = 3 (4 JESD lanes), lanes 0-3 are enabled (yes, I've tried to enable all lanes).
M = 1 (2 streams per frame)
F = 0 (1 octet in the frame)
K = 19 (20 frames in multiframe)
SYSREF is 39.0625 M, but it is disabled, according to Initialization Set Up.
I've also tried to reset DAC through RESETB pin - registers became default, then I programmed it again - that didn't help.

Below's our config for reference.

4353.cfg

Thanks in advance!


Kind Regards,

Jejomar