Hello All,
I'm working with DAC38J82 in a customised hardware. I'm having an issue in getting the DAC output. Here is my configuration.
DAC input clock is 2457.6MHz. DAC PLL is not used. No SYSREF input.
I'm trying to use the DAC in 421 (LMF) mode. I'm generating complex samples in FPGA with 153.6MHz sampling rate and the corresponding lane rate is 1536Gbps (153.6MHz*16*2*1.25/4).
I'm using 16x interpolation (153.6MHz*16 = 2457.6MHz) and hence DAC update rate will be 2457.6MHz. NCO and mixer is enabled and 300MHz as NCO frequency.
Lane 0 - 3 is used. patha output should be plated in DACA and pathb output should be played in DACD. So DACB and DACC is kept in sleep.
Here is my testing sequence.
1. Generated the required clock for the DAC and FPGA. For DAC clock LVPECL standard clock is generated.
2. Initialize the FPGA JESD core and generating K28.5 (BC character).
3. DAC hardware reset toggled from 0 to 1.
4. DAC sleep pin kept to 0.
5. Configured the DAC in 3-pin SPI as given below.
6. Transmitting the CGS & ILA Phase data in FPGA as per the state of SYNCB differential input.
7. Enabled the DAC output with the hardware TXENABLE input.
8. Monitored the lane error status in registers 0x64,0x65,0x66 and 0x67. All are 0x1 (FIFO empty flag).
9. Monitored the error count of all four lane and it is 0x0.
10. Monitored the series block0 PLL out of lock status in 0x6C. It is 0x7. So serdes block0 PLL is in lock.
No output in DAC in 300MHz. In FPGA complex input I is kept as 0x7FFF (positive full scale in 2's complement) and Q is ket as 0x0000 (e^(j0)). So I should get a CW at the NCO frequency.
Kindly look in to the DAC configuration sequence and provide your valuable feedback at the earliest.
DAC Configuration sequence as follows.
x”020001“,
x”000818“,
x”010003“,
x”022052“,
x”03A300“,
x”040000“,
x”05FF03“,
x”06FF00“,
x”070000“,
x”080000“,
x”090000“,
x”0A0000“,
x”0B0000“,
x”0C0400“,
x”0D0400“,
x”0E0400“,
x”0F0400“,
x”100000“,
x”110000“,
x”120000“,
x”130000“,
x”140000“,
x”150000“,
x”161F40“,
x”170000“,
x”180000“,
x”190000“,
x”1A0026“,
x”1B0000“,
x”1E1111“,
x”1F8880“,
x”200000“,
x”221B39“,
x”2301FF“,
x”240000“,
x”25A000“,
x”260000“,
x”2D0000“,
x”2EFFFF“,
x”2F0004“,
x”300000“,
x”311000“,
x”320000“,
x”330000“,
x”340000“,
x”3B1800“,
x”3C0028“,
x”3D0088“,
x”3E0168“,
x”3F0000“,
x”460044“,
x”47190A“,
x”4831C3“,
x”490000“,
x”4A0F3E“,
x”4B1300“,
x”4C1303“,
x”4D0100“,
x”4E0F4F“,
x”4F1CC1“,
x”500000“,
x”5100FF“,
x”5200FF“,
x”530000“,
x”5400FF“,
x”5500FF“,
x”560000“,
x”5700FF“,
x”5800FF“,
x”590000“,
x”5A00FF“,
x”5B00FF“,
x”5C1100“,
x”5E0000“,
x”5F0123“,
x”604567“,
x”610011“,
x”640000“,
x”650000“,
x”660000“,
x”670000“,
x”680000“,
x”690000“,
x”6A0000“,
x”6B0000“,
x”6C0000“,
x”6D0000“,
x”6E0000“,
x”6F0000“,
x”700000“,
x”710000“,
x”720000“,
x”730000“,
x”740000“,
x”750000“,
x”760000“,
x”770000“,
x”780000“,
x”790000“,
x”7A0000“,
x”7B0000“,
x”7C0000“,
x”7D0000“,
x”4A0F21“;
Thanks
Loganathan N
