ADC12DJ5200RF: Registers to improve JESD lane performance

Mark Whittington

Part Number: ADC12DJ5200RF

Hello,

I have a custom board that is using the ADC12DJ5200RF. We are seeing some errors on the JESD link that we have been trying to resolve. It is a 2 board system with an FPGA on one board and the ADC on another. If we replace the custom ADC board with the TI Eval board we do not see errors so it seems clear there is something degraded on the custom board.

In the course of troubleshooting I was scouring these forums and found someone reference registers that are not listed in the datasheet.

Specifically they noted that they set the following:

0x4F = 0x1F

0x4D = 0x41

When I set these registers with the above settings all my JESD errors went away. This also resulted in a notable improvement in the eye diagram.

Can you explain what these registers are doing? Is there any issue with setting them different than the default value? Could I optimize my link even more with different values?

Thanks.

Mark

over 2 years ago

0 Neeraj Gill over 2 years ago

TI__Mastermind 20541 points

Hi Mark,

Can you please specify your which silicon you have on the board by reading the register address 0x6. Also you point me to the forum post which was talking about the above register writes.

Regards,

Neeraj

0 Mark Whittington over 2 years ago in reply to Neeraj Gill

Intellectual 460 points

Hello Neeraj,

The previous post I was referring to can be found at the link below:

https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1001415/adc12dj5200rf-jesd204c-has-crc-errors?tisearch=e2e-sitesearch&keymatch=ADC12DJ5200RF%20crc#

Thanks.

Mark

0 Neeraj Gill over 2 years ago in reply to Mark Whittington

TI__Mastermind 20541 points

Hi Mark,

Mark Whittington said:
0x4F = 0x1F

0x4D = 0x41

These register were only needed for previous silicon revision of the ADC. But you have the latest silicon revision of the ADC so you don't need these register settings.

The only setting you need to play is the 0x0048 0x03 // Set serializer pre-emphasis to 3 .

Regards,

Neeraj

0 Mark Whittington over 2 years ago in reply to Neeraj Gill

Intellectual 460 points

Hello Neeraj,

Unfortunately this is empirically not the case. When I run my JESD link with the default settings for registers 0x4F and 0x4D, I get regular bit errors. A continuous ILA test shows errors on all lanes within a few seconds.

Changing the pre-emphasis to 3 did not improve the situation.

changing the 0x4F and 0x4D values as specified above resolved all the errors.

Can you answer my original questions?

1. What are these registers doing? I want to know this in order to possibly optimize further instead of blindly selecting the values from the previous post.

2. Is there any problem with using the updated values? Am I over-stressing the part?

Thanks.

Mark

0 Neeraj Gill over 2 years ago in reply to Mark Whittington

TI__Mastermind 20541 points

Hi Mark,

Lets take this conversation offline. Will email you and talk the conversation offline.

Regards,

Neeraj

0 Mark Whittington over 2 years ago in reply to Mark Whittington

Intellectual 460 points

For E2E posterity, I was able to get the link working without adjusting the stated registers by adding more local bypassing directly under the power vias of the ADC on the 1.1V DVDD net.

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ADC12DJ5200RF: Registers to improve JESD lane performance