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ADC12DJ5200RFEVM: Does it work with a Xilinx FPGA?

Part Number: ADC12DJ5200RFEVM
Other Parts Discussed in Thread: ADC12DJ3200EVM

Hello!

I'm starting a project where I need to connect a high speed ADC and high speed DAC to an FPGA.  The system could be like this:

ADC -> (FMC) -> FPGA  -> (FMC) -> DAC

Ideally, ADC and DAC should achieve  at least 6 GSPS so I think that ADC12DJ3200EVM and ADC12DJ5200RFEVM could fit.

FPGA could be ZCU102  (2 FMC with 8 GTH each one) or Another option could be use a VCU118 or an ada-sdev-kit2 and a FMC splitter.

In addittion, I would like to know if I could achieve 10 GSPS using 8 JESD204b lanes. I've looked at the datasheet (page 103 and 104) And I've found three options JMODE 30 (with 12 bit resolution) and JMODE5 and JMODE44 (with 8 bit resolution) that could fit, am I right?

Finally I wanted to check which pins are routed to the FMC on  ADC12DJ5200RFEVM. I've looked for the schematic, but I found that one that it's suppose to have a ADC12dj5200 but if you look inside the schematic the chip is an ADC12DJ3200AAVR https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/979172/adc12dj5200rfevm-revision-c-design-file

By the other hand, if I get ADC12DJ3200EVM, i think the most suitable modes to achieve 6,4 GSPS with 8 lanes are JMODE 0 (12 bits) and JMODE 5 (8 bits) Am I right?

But I have the same problem, I don't know if is suitable to use it with ZCU102, because I don't know if the ADC FMC pins fit with the FPGA FMC pins... I would need the schematic to verify it...

To summarize:
Could I achieve 10,4 GSPS with ADC12DJ5200RFEVM using 8 lanes of JESD204 and using mode 30, 5 or 44?

Could I achieve 6,4 GSPS with ADC12DJ3200EVM using 8 lanes of JESD204 and using mode 0 or 5?

Are the FMC pins fit with ZCU102ada-sdev-kit2, or VCU118?

Thank you!