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ADS124S08: All channel data acquisition

Part Number: ADS124S08

question1:I AM PROGRAMMING THE IC from FPGA.

configuration:

1.Continous conversion mode

2.800 sps

3.PGA 32 GAIN

4.LOW LATENCY FILTER

5.Delay ...>1*tmod

how to program the ic for getting the data from remaining 5 channels as we are using differential inputs. can you help us in flow for acquiring the data for remaining  5 channels.

For acquiring the single channel data i am using following flow:(for single channel working fine).

1.write the data to configuration registers. I am using first five registers and writing sequentially one after the other(1(status reg),2(mux reg),3,(pga),4(data rate reg),5(ref reg ).

   while writing to registers sart/sync low

6.start/sync high,      waiting for 28 t clk cycles

7.start/sync low,  checking for DRDY to be low

8.data acquisition.

9.going back to 1 

For second channel reading:

i am following the same flow as shown above for reading the second channel with 9 step address increment.initilally i am making address as zero(before step 1) and send 01 value to mux register and completing one read.

so in step 9 ,channel counter will increment by1 and goes to step 1 i am keeping all reg values as same except mux reg which are 23 and sending the value.

but i am not able to get the readout.

hence request you to help me in complete flow for reading all channels .....