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ADS127L01: Resolution mode conversion issue

Cherry Zhou
Mastermind 22235 points
Part Number: ADS127L01

Issue:

With the HR pin tied low, when converting the EXT terminal external resistance from 120K to 60.4K, that is, when switching VLP mode to LP mode, it does get higher in power consumption, but the output noise of the ADC is not improved.

But at this point the AFE front end equivalent self-noise and the theoretical output noise of the ADC are essentially equal, so the overall equivalent self-noise output should be somewhat reduced after switching mode.

The customer would like to know what's the possible reason for that. Thanks!

Best Regards,

Cherry Zhou

  • 0
    TI__Mastermind 46200 points

    Hi Cherry,

    Switching REXT from 120k to 60k has very little impact on the total noise in the ADC.  It does slightly reduce the noise in the internal amplifiers, but the thermal noise from other internal components dominate the total ADC noise.  The purpose of increasing power (reducing REXT) is to support higher input clock frequency and higher output data rates.  Decreasing REXT increases the internal amplifier bandwidth which results in shorter settling times needed to support higher output data rates.

    The maximum Fclk in VLP mode is 4.4MHz.  Reducing REXT to 60.4k (increasing total power) allows Fclk to increase up to 8.8MHz.  For the same OSR setting, you can now operate at 2x the output data rate.

    Table 1 in the datasheet confirms that the noise does not change for the different power modes; it mostly depends on the OSR setting.  For example, OSR=256, WB2 filter, in all cases, the noise is approximately equal to 3.5uVrms (there is some variation as Fclk increases).

    Regards,
    Keith Nicholas
    Precision ADC Applications

  • 0 in reply to Keith Nicholas
    TI__Mastermind 22235 points

    Hi Keith,

    Thanks for your reply!

    The customer would like to confirm the following info:

    1. OSR is the main determinant of ADC output noise.  If the same FCLK is used, is it not possible to improve the output noise of the ADC through mode conversion of VLP-LP-HR?

    2. If the customer would like  to get lower ADC noise at the same sampling frequency, change the OSR accordingly after changing the FCLK according to the figure you given, is that right?

    Thanks again!

    Best Regards,

    Cherry

  • 0 in reply to Cherry Zhou
    TI__Mastermind 46200 points

    Hi Cherry,

    1.  Yes, that is correct.  The internal noise of the ADS127L01 does not improve when using the different modes for the same FCLK, OSR, and Filter setting.  Operating Fclk at a lower frequency does allow more time for the external reference and amplifier to settle, so it may improve the overall noise due to external components, but it will not improve the noise of the ADC.

    2.  Yes, the lowest noise for the ADS127L01 is when using the highest OSR setting.  For example, using Wideband filter 2 and output data rate of 64ksps, you can either operate in HR mode with OSR=256 and Fclk=16.384MHz (SNR=113.9dB), OR, operate in VLP mode with OSR=64 and Fclk=4.096MHz (SNR=108.3dB).

    Regards,
    Keith

  • 0 in reply to Keith Nicholas
    Prodigy 95 points

    Hi, I'd like to continue this thread; The datasheet mentions only the very precise values of 60.4k and 120k, but I guess that I could reduce REXT below 60k to increase the current and then also be able to push the maximum frequency up a bit? I am aiming for 18.432 MHz.

    Thanks.

  • 0 in reply to DanielU
    TI__Mastermind 46200 points

    Hello,

    It is best not to operate outside the specified conditions for the ADS127L01, including the bias resistor value and the maximum CLK frequency. 

    The ADS127L01 is specified for a CLK frequency up to 17.54MHz.  Although you can increase this value and will likely get good performance in the lab on a random number of devices, you could run into problems in production runs over large samples of devices due to process variation.

    Regards,
    Keith Nicholas
    Precision ADC Applications

  • 0 in reply to Keith Nicholas
    Prodigy 95 points

    Thanks. Yes, I agree, but there are not always good parts available and sometimes a clever engineer has to use parts out of spec and take the associated risk. In this project it is so far only an idea at the prototyping stage. I tried REXT at 47k and clocked it at 18.432 and got something out of the chip at least. Let's see if it meet my goals on spec!

  • 0 in reply to DanielU
    TI__Mastermind 46200 points

    Hello,

    Understood. Just keep in mind when operating outside of the specified conditions that many of the min/max specifications in the datasheet may not be met. 

    Regards,
    Keith