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ADS6148 self-test mode

Jade Lee
Prodigy 110 points
Other Parts Discussed in Thread: ADS6148, ADS6129

Hi there, 

I have a question about ADS6148 self-test mode.

 

My customer is using ADS6148 and meets an issue about digital error code of ADS6148.

the customer mentions that he will see an digital error code every 2M digital data when the input signal is 1MHz analog sine wave. 

I ask he to use self-test pattern to see if there is any digital error code and everything is fine.

I want to use this self-test mode to prove that ADS6148 itself is fine and the issue is related to the schematic of his design. 

However, the customer complains this self-test experiment only can guarantee the digital path of ADS6148 is fine but can't guarantee the A-to-D path of ADS6148 is fine.

I would like to know the principle of the self-test mode of ADS6148 and whether the self-test can guarantee the clock and ADS6148 itself are ok?  

 

Thank you :) 

 

 

  • 0
    TI__Mastermind 29220 points

    Hi,

    The customer is correct on this point, the test pattern modes are useful for verifying the digital connection from the ADC to the FPGA or ASIC that is receiving the data - letting the FPGA designer check that they have their design correct for things like meeting setup/hold time or getting the bit-ordering correct.   The test pattern modes are inserting digitally created test patterns near the output of the device - this data path is not going through the pipeline stages of the data converter.

    There is a spec in some of our data sheets for bit error rate, which refers to the probability that a bit of a sample might be erroneous (also sometimes called sparkle).   I do not see this specification in the ADS6148 datasheet, but I saw from the design team about  a month ago for the ADS6129 (same basic design except 12bit)

    - What is the designed value of BER of ADS6129?            Ans: ADS6129 is expected to be better than 9e-9.

    That would mean we expect about 9 errors in 10^9. 

    An error code in every 2M samples would be higher than the expected bit error rate of 9e-9, but the probability of a bit in error is not completely random or uniform.  Since the ADC is a pipelined device, some codes are more likely to be in error because of a code magnitude just crossing the threshold between pipeline stages, and if a customer is inputing a signal that just hits this magnitude frequently then the observed bit error rate may be higher.  If the input data is set to just under full scale so that all the sample codes are possible then the observed bit error rate should be in line with what we expect. 

    Regards,

    Richard P.