ADS5402: ADS5402

Hi Kerry,

See my comments below to your questions:

Regards,

Rob

1. What tolerance does each data diff pair within a channel have to be matched with respect to other pairs within the channel? RR: matching both outputs are critical, intra-pair (P n N) but 5-10mils is fine (between any PnN pair). Within one channel, the LVDS pairs can have a tolerance, 100mils or so (between the longest and shortest pair within one channel). As you go from channel to channel the delta there can be a bit bigger, 200-300mils (between the longest and shortest pair between the two channels). Therefore, there is no need to do lots of "tromboning" of traces to keep everything equal-distance.

It kind of comes down to timing requirements for setup and hold times to be valid during the data capture at the receiver side. If the ADC is sampling at 800MSPS, then the duty cycle is 1.25nSec. Just to give a quick reference on what that means in terms of timing, one can reasonably assume a trace has 2nSec/foot prop delay on standard FR4. There are plenty of PCB calculators out there on the internet can "dial" this number in based on pcb stackup details you plan to use for your design.

2. What tolerance does the data diff pairs within a channel need to to the clock? 100 mils? RR: yes, 100mils if more than suffice.

3. What does channel A data outputs signals need matched with respect to channel 2 data outputs. RR: yes, see the explanation above.