Hi everyone,
The 'Power Supply' page in ADS42JB69EVM design shows that it converts '5VIN' DC voltage to '4V' with 'TPS54319' module, and then change '4V' to '1.8V' with 'TPS7A4700' module(Figure 1).
My question is why not change '5V' to '1.8V' directly with 'TPS7A4700' or 'TPS54319' like '5V - 3.3V' in same page(Figure 2).
Hi Jim,
Another question, I saw that 'SEN' pin has an internal 150KOHM pull up resistor in ADS42JBxx datasheet(Figure 1) .
So why another external pull up 1KOHM resistor is added in ADS42JB69EVM design(Figure 2) ?
Nan
Hi Jim,
I want to ask another question about your design,
It's about JESD204B Subclass 1,,, uh,,, SYSREF,
I have seen that you mark "JESD CORE CLOCK & JESD CORE SYSREF PAIRS HAVE MATCHED LENGTH" in your design(Page 3 LMK04828), and I know it's for equal length.
So my question is why not set all the clock output lines equal length both ADC's and FPGA's clocks(as below figure)?
Regards,
Nan
