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ADS8528: SPI clock scheme

Marko Gulin
Intellectual 430 points
Part Number: ADS8528
Other Parts Discussed in Thread: TMS320F28335, ADS8568

I am confused by the SPI clock polarity and phase on ADS8528.

In the datasheet (SBAS543C pp. 33) it says:

Starting with the most significant bit (MSB), the output data are changed with the SCLK falling edge.

Serial data input SDI are latched with the SCLK falling edge.

So from the MCU perspective:

- the MCU outputs data on rising edge since ADS8528 latches data on falling edge

- the MCU latches data on rising edge since ADS8528 outputs data on falling edge

Here are the supported clocking schemes for TMS320F28335 (SPRUI07 pp. 558):

Falling edge without delay. The SPI transmits data on the falling edge and receives data on the rising edge of the SPICLK.

Falling edge with delay. The SPI transmits data one half-cycle ahead of the falling edge and receives data on the falling edge of the SPICLK.

Rising edge without delay. The SPI transmits data on the rising edge and receives data on the falling edge of the SPICLK.

Rising edge with delay. The SPI transmits data one half-cycle ahead of the rising edge and receives data on the rising edge of the SPICLK.

Does this mean I have to change the clocking scheme on the master (MCU) after I write configuration? More specifically:

- to write configuration to ADS8528, I would use Falling edge with delay

- to read configuration and data from ADS8528, I would use Falling edge without delay

It is not mentioned in the datasheet, but from the diagrams I assume that the serial clock should idle at high. That is why I only mention the "falling edge" clocking schemes. Please correct me if I am wrong.

This is the first time I need to change clocking scheme for read and write operations. Can you please confirm this conclusion?

If I am correct about this, what would be the reason for this clocking scheme implementation on ADS8528? Why not using single clocking scheme for both read and write operations?

Let me give some perspective how I realized this in the first place.

I first configured the clocking scheme to work for "write configuration". I was reading back the configuration using the same clock scheme and it worked until I did some minor non-SPI-related change in the code.

What I mean when I say it did not work is that configuration I was reading back was not as expected. It seems the entire configuration was bit shifted to the left by 2. Again, this problem appeared only when I did some minor non-SPI-related change in the code.

Then I read the datasheet for ADS8528 again and figured the clocking scheme is different for read and write operations. I implemented this new logic and it seems to work, but I would still like to get confirmation.

  • 0
    TI__Mastermind 25020 points

    Hello Marko,

    The device uses CPOL =1, and CPHA = 1 communication protocols. The below image provides a visual representation of the available modes. 

    This means the ADC launches, or changes, SDI on the falling edge. The ADC also captures, or reads, data on SDI on the falling edge. The SCLK, as you noted idles high.  

    If you program your MCU to match this,  CPOL =1, and CPHA = 1, you should more easily read and write to the device. 

    Regards

    Cynthia

  • 0 in reply to Cynthia
    Intellectual 430 points

    Hi Cynthia,

    Please note that I am not struggling with understanding how different SPI clock schemes work. What I am trying to say is that single clock scheme does not fit both cases, at least according to the datasheet.

    In the picture you showed both data lines (MISO and MOSI) are changed on one edge and latched on the other. ADS8528 apparently both outputs and latches data on the same edge (falling), which is something I have never seen before.

    The CPOL=1 and CPHA=1 corresponds to "Falling edge with delay" in the original post. Here is what happens with the two data lines with respect to clock edges:

    - MCU-SIMO --> ADC-SDI is changed on rising edge and the ADC latches data on falling edge. This is clear as I have already explained.

    - MCU-SOMI <-- ADC-SDO is changed on rising edge and the MCU latches data on falling edge. This is not consistent with ADS8528 datasheet and what you wrote in your post:

    Starting with the most significant bit (MSB), the output data are changed with the SCLK falling edge. [Datasheet]

    This means the ADC launches, or changes, SDI on the falling edge. [Your post. You probably meant SDO and not SDI?]

    In case of CPOL=1 and CPHA=0, which corresponds to "Falling edge without delay" in the original post, the situation is as follows:

    - MCU-SOMI <-- ADC-SDO is changed on falling edge, and the MCU latches data on rising edge. This is consistent with the two quotes above - [Datasheet] and [Your post].

  • 0 in reply to Marko Gulin
    TI__Mastermind 25020 points

    Hello Marko, 

    I made a mistake in my previous post, please see below for the correction, apologies for the misunderstanding. 

    "The device uses CPOL =1, and CPHA = 0 communication protocols. The below image provides a visual representation of the available modes. 

    This means the ADC launches, or changes, SDI on the falling edge. The ADC also captures, or reads, data on SDI on the falling edge. The SCLK, as you noted idles high.  

    If you program your MCU to match this,  CPOL =1, and CPHA = 0, you should more easily read and write to the device. "

    It seems your understanding is spot on!

    Regards

    Cynthia 

  • 0 in reply to Cynthia
    Intellectual 430 points

    Hi Cynthia,

    Thank you for your reply.

    In my previous post I explained in detail why neither CPOL=1 CPHA=1 or CPOL=1 CPHA=0 fits what is described in the ADS8528 datasheet and what you wrote in your first (and second) reply:

    In the picture you showed both data lines (MISO and MOSI) are changed on one edge and latched on the other. ADS8528 apparently both outputs and latches data on the same edge (falling), which is something I have never seen before.

    The CPOL=1 and CPHA=1 corresponds to "Falling edge with delay" in the original post. Here is what happens with the two data lines with respect to clock edges:

    - MCU-SIMO --> ADC-SDI is changed on rising edge and the ADC latches data on falling edge. This is clear as I have already explained.

    - MCU-SOMI <-- ADC-SDO is changed on rising edge and the MCU latches data on falling edge. This is not consistent with ADS8528 datasheet and what you wrote in your post:

          Starting with the most significant bit (MSB), the output data are changed with the SCLK falling edge. [Datasheet]

          This means the ADC launches, or changes, SDI on the falling edge. [Your post. You probably meant SDO and not SDI?]

    In case of CPOL=1 and CPHA=0, which corresponds to "Falling edge without delay" in the original post, the situation is as follows:

    - MCU-SOMI <-- ADC-SDO is changed on falling edge, and the MCU latches data on rising edge. This is consistent with the two quotes above - [Datasheet] and [Your post].

    I will emphasize one more time the most important part:

    ADS8528 apparently both outputs and latches data on the same edge (falling). SPI slave devices usually output data on one edge and latch data on the other edge, but ADS8528 does both operation on the same edge.

  • 0 in reply to Marko Gulin
    TI__Mastermind 25020 points

    Marko, 

    I agree that the timing schematic in the datasheet does not align edges directly to each other, but the timing specifications adds the more detail. 

    Refer to the serial timing in Figure 1 of ADS8568 datasheet, SCLK level is '1' for idle status, so the clock polarity CPOL=1,
    the ADC will latch or read data at the falling edge of SCLK which is the first edge, so clock phase CPHA=0,

    Note that the set up and hold time are all in reference to the SCLK falling edge.  

    Also, in the users guide for the ADS8568EVM, which is the 16 bit version of the device, it states that CPOL =1, CPHA = 0 must be used to communicate for this family of devices.  

    Have you tried these communication methods and it not work properly? 

    Regards

    Cynthia