DAC5675A-SP: driving the clock pins with LVDS signal

Hi York,

maintaining VCM and Swing could be a problem if LVDS is used. Usually, FPGA's can do  LVPECL, is there a reason for LVDS?

Miguel, Thanks for the answer.  We are using ADA-SDEV-BASE - FPGA Board to generate the clock.  Our original plan is to generate all DAC inputs and CLK, CLKC with LVDS.  No issues with the DAC inputs but since CLK and CLKC need LVPECL, I can ask our FPGA engineer to see if he can generate LVPECL CLK and CLKC.  Or better yet, can you recommend a LVDS to LVPECL translator?  Since we are using 3 ea DAC5675A, it would be ideal to use a triple LVDS to LVPECL translator chip, does TI such a device?  We'll take a quad in/out device since triple in/out is not too common.  If you don't have any triple or quad LVDS to LVPECL translator device, please recommend the best single LVDS to LVPECL translator chip.  Thx

Hi York,

we have a limited selection for space grade clock buffers. please see link below.

https://www.ti.com/clocks-timing/buffers/products.html#p404=Differential&p1498=HiRel%20Enhanced%20Product;Space

Also, another solution can be using circuitry to achieve LVDS to LVPECL. 

Do you know the volume of units that will be ordered for this project?

Miguel,

I reviewed the clock buffer CDCLVP111-EP spec and it's not what we need, if I read the data sheets correctly, the CDCLVP111-EP is a 1:10 LVPECL buffer.  What we need is a LVDS to LVPECL translator.  I wonder if SN65LVDT101 will work for us?

You also mentioned "Also, another solution can be using circuitry to achieve LVDS to LVPECL", I am not sure what you are referring to?

This is a "LEO" project so the volume is low (< 100).

Please let us know your thoughts.  

Link has below has termination configurations.

https://www.ti.com/lit/an/scaa059c/scaa059c.pdf

SN65LVDT101 will work, however it's not space grade. 

Did your FPGA designer answer whether they can support LVPECL? I'm not sure what peripherals will be used in the FPGA but Kintex Ultrascale does have LVPECL configuration

Thanks, I'll ask our FPGA designer regarding LVPECL support. 

Does SN65LVDT101 has an "EP" version?  Our end product will be on "LEO" mission and I was told that EP will work in that scenario.

The data sheet does not mention it but I am listening to a TI webinar about "enhanced space plastic products" so hopefully procuring SN65LVDT101 in EP is not an issue in the near future

The fastest way to get an answer for that is posting a question in the interface forum. Please see link below.

https://e2e.ti.com/support/interface-group/interface/f/interface-forum