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TSW14J56EVM: ADS52J90 interface with TSW14J56

Part Number: TSW14J56EVM

I am in the process of compiling the source code of TSW14J56RevD Respin FW on Quartus 18.1.0. So far everything works and I can load the code in the .sof (SRAM object file) into the FPGA via JTAG and it seems to work. However, for the HSDC Pro program I need the .rbf (raw binary file). But I cannot create the .rbf via Quartus Prime Standard Edition under ->File -> Convert Programming File because the following error message appears:

Error (210039): File C:/ws/TSW14J56_VNA/trunk/Altera_JESD204B/jesd204b_refdesign/syn/AVGZ_gen_jesd204b_120_SP2_external_memory/jesd204b_time_limited.sof contains one or more time-limited megafunctions that support the Intel FPGA IP Evaluation Mode feature that will not work after the hardware evaluation time expires. Refer to the Messages window for evaluation time details.

How can I creat a .rbf in this situation? I need it because I want to add decimation filters in the datastream sent to the FX3 interface

Thomas