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ADS8568: Can't get the configuration register to output when enabling the read-out access register

Théophile Vanhée
Prodigy 10 points
Part Number: ADS8568

Hi,

I have an issue trying to get the config register to read-out.

I'm using Software and Serial modes. I'm also trying to use the ADC with all 4 channels active, the CONVST signal is linked to all 4 CONVST pin of the ADC.

After sending this config (0xFFFCE3FF) with READ_EN set I don't have any reply as shown below :


Also there seems to be 2 random bits set during the first and the 3rd exchange. I don't know why.

I have also tried sending the configuration, then setting the CONVST signal and after that reading the SDO_A by sending 0x00000000 on the SDI channel.
But the results are inconsistent, different tries give different results with the exact same code and connections.

I can't really figure out where is the problem coming from.
After reading the answer to this question I thought it might be coming from the way I handle the CONVST signal :

"ADS8568 needs two accesses (conversions activated by CONVST_x) to output Configuration Register contents to SDO_A line"

But it is not really clear to me what is meant by it. In my case conversion have been activated and I did 2 accesses.

Should I use the CONVST signal differently ? Is there something I'm missing in the usage of the read-out ?

Also I made sure that my SPI config is Polarity = 1 and Phase = 0.


Regards,

Théo

  • 0
    TI__Mastermind 24970 points

    Hello Theo, 

    Would you capture a scope shot with the clock please? It is interesting that the same command has different results, this likely means that communications is not stable/consistent. 

    please include SDI,SDO,CLK, and CS

    To address your question about "ADS8568 needs two accesses (conversions activated by CONVST_x) to output Configuration Register contents to SDO_A line" The device needs bit 30 in the configuration register to be set high to enable read out. After this you will need two accesses, or you can think of it as frames, of CONVST.

    Regards

    Cynthia 

  • 0 in reply to Cynthia
    Prodigy 10 points

    Hello Cynthia,

    Thanks for the firsts answers.

    Here is a capture with the clock.

    It might be worth saying that I am using the ADS8568EVM-PDK Evaluation Module for my tests.
    And on this board there is a reset button. I noticed that when I press it (with my code controlling the SPI still running), I'd often get the result on the first picture. Here the ADC is sending back the configuration SDI but it happen on the same cycle as the one I'm sending the configuration which seems strange.

    Also this result is not consistent and sometimes the ADC respond with seemingly random bits. See the capture below:
    Between those 2 captures I only reset the ADC yet the response vary greatly.

    Ok so for my question about CONVST, I should be getting the read out on the very next 32b communication frame after sending the configuration register with the bit 30 set. Which should be where I putted "1st access" and "2nd access" on the first picture. Am I understanding this right ?

    Regards,
    Théo

  • 0 in reply to Théophile Vanhée
    Prodigy 10 points

    While I was doing further testing trying to get a clean read-out. I still seem to get the response on the same accesses that the one I send the configuration register but I noticed the bit 31 (WRITE_EN) was not set in the answer.

    This can be seen on the first picture I send on my last post. I sent 0xFFFCE3FF and got 0x7FFCE3FF.

    Is it normal for the ADC to send back the configuration without this bit ?

    Regards,

    Théo

  • 0 in reply to Théophile Vanhée
    TI__Mastermind 24970 points

    Hello,

    It is not good practice to continue to communicate with the device WHILE resetting it. This could lead to the device being in an unpredicted state. meaning the device is taking in information that the user believes is being interpreted one way, and the device is interpreting it differently.  

    One suggestion is to use the EVM GUI to communicate to the hardware and use a scope to observe the digital timing/communications and compare that to your own.

    Another suggestion is after pressing the RESET pin for 50ns (without any SPI commands), set the first communication to the device to read the register content, at this point it should read 000003FFh, as this is the default after reset. This can help to start narrowing down the issue. 

    An access or frame is when CS/FS is brought low, thus you will need two FS frames. 

    Regards

    Cynthia