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DAC38J84EVM: Why the data lines are jumbled up?

S Majumdar
Prodigy 30 points
Part Number: DAC38J84EVM
Other Parts Discussed in Thread: DAC38J84

Hello,

The data lines from FMC to the DAC are jumbled up. For example, DP5_C2M from FMC is connected to RX7. It is true for other data lines also. Why is it connected this way? Please forgive me if it is a silly question.

Regards,

S. Majumdar

  • 0
    TI__Guru 66004 points

    Hi Majumdar,

    It has to do with the TSW14J56/57 EVM. Our FPGA EVM has the GPIO mapped to single bank of the Intel based FPGA, and hence the routing to the DAC38j84 is mapped according to the usage of the TSW14J56/J57. This is to ensure optimal timing constraint can be set up in the Intel reference design. 

    -Kang

  • 0 in reply to Kang Hsia
    Prodigy 30 points

    Hi Kang,

    I am trying to connect the DAC38J84 EVM to an Arria 10 SoC board. The data lines are already fixed by the FMC standard. But in the DAC EVM, DP5_C2M is going to RX7 instead of RX5 (same for other data lines). So, what care should I take when I am interfacing this EVM to an FPGA board other than TSW14J56/57?

  • +1 in reply to S Majumdar
    TI__Guru* 91947 points

    Majumdar,

    Just make sure when doing your FPGA pin assignment, the pins are mapped properly per what the IP core is expecting. Make sure the data bits are in correct order along with the P & N for each serdes lane. Remember that the order can be scrambled and then unscrambled using register settings inside the DAC if needed. This includes the P & N along with data bit numbering, using register addresses 0x3F, 0x46-48, 0x4A, 0x5F and 0x60. 

    Regards,

    Jim 

  • 0 in reply to jim s
    Prodigy 30 points

    Hi Jim,

    Sorry for the delay in response. I could connect the EVM with the Arria 10 SoC board. Thanks a lot.

    Regards,

    S. Majumdar