Dear Team,
A related question to: e2e.ti.com/.../ads1251-sigma-delta-switching-frequency-synchronization
"Since I am using 100% of FPGA pins, I am summing clock,serial clock, the same for all chips. And just MISO pins will be different for each channel. If I use the same timing on all channels, does that mean it will be synchronized all the time ?
I can pull back timing if needed, all I care is to get 1kHz sampling rate ( or oversample in hardware as much as possible to get even more better noise floor)"
Can you offer any advice?
Thank you,
Daniel