Q1. I am programming the IC from FPGA with following steps:
step 1. start(pin)=0.
step 2:writing to power register
step3: writing to interface register
step4: writing to mode0 register
step5:writing to mode1 register
step6:writing to mode2 register
step7:writing to inputmux register
step 8:start(pin)=1 and stopping the sclk.
step 9:waiting for drdy to low, if low go to step10 otherwise in step 9
step 10:read the data 32 bit.......starting the sclk and send 32 sclk cycles to read
step 11:going to 8.
data needs to be completely read out of the ADC at least 16 tCLKs before DRDY drops low again(page no 68, figure 108 , point 3).Request you to elaborate this timing restriction ,how to read within 16tclk when we need to receive 32 bit data(32 tclk).