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ADS1262: READ Data Problem

Part Number: ADS1262

Q1. I am programming the IC from FPGA with following steps:

step 1. start(pin)=0.

step 2:writing to power register

step3: writing to interface register

step4: writing to mode0 register

step5:writing to mode1 register

step6:writing to mode2 register

step7:writing to inputmux  register

step 8:start(pin)=1 and stopping the sclk.

step 9:waiting for drdy to low, if low go to step10 otherwise in step 9

step 10:read the data 32 bit.......starting the sclk and send 32 sclk cycles to read

step 11:going to 8.

 data needs to be completely read out of the ADC at least 16 tCLKs before DRDY drops low again(page no 68, figure 108 , point 3).Request you to elaborate this timing restriction ,how to read within 16tclk when we need to receive 32 bit data(32 tclk).

  • Hi Ponraj,

    Per your other question, this is just saying that the data needs to be completely read out of the ADC at least 16 tCLKs before DRDY drops low again. This is basically a timing restriction. If you are still clocking out data within 16 tCLKs of DRDY dropping low, that data may be invalid. You absolutely do need to issue 32 SCLKs in order to get data from the ADC each time. But you should issue these SCLKs as soon as DRDY drops low, which should avoid the 16-tCLK timing restriction you are concerned about.


  • Hi bryan,

    As i am a beginner in ADC data acquisition ,request you to elaborate little more with some timing diagram or by taking an example for reading to satisfy this timing restriction of 16 tclk before drdy low.

    a)how to connect reset/pwdn pin? i.e we can make it high continuously during power on itself or as per the data sheet we need to keep the pin low for 4 tclk(min) and make it high???

    b)How to program the IC ,i mean flow for programming the ic through din and reading the data from the ic. i want to read by controlling start pin .so when to make start pin high and low for corresponding drdy low and high for data acquisition.

  • Hi Ponraj,

    There is a flow chart (Figure 10-16) that discusses the necessary steps for programming the ADC. Please follow these steps to get the ADS1262 up and running.

    I would encourage you to use "read data by command" mode (Section as then the 16 tCLK restriction does not apply.

    RESET/PWDN can be left high unless you actually do want to reset or power down the ADC. Typically this pin would have a pull-up connected to DVDD to keep it high, especially during power-up.