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DAC38J84EVM: Questions for DAC design with a 3rd party evaluation FPGA board

Part Number: DAC38J84EVM

I'm designing my third-party FPGA( XILINX Zynq UltraScale+ XCZU9EG  MPSoC ) evaluation board with a standard FMC-HPC connector,which is not in the support list of HSDC pro software.

My question is following:

1.weather and how can I connect my   third-party FPGA evaluation board to the HSDC software? Is it possible to recofigure the FPGA source code developped for  TSW14J01 or VC707 / KC705 / ZC706 plus TSW14J10?

2.BESIDE standard jesd204b protocol which has clk pins and tx pins, the DAC38J84EVM board FMC connector also has pins (named FMC_SCLK, FMC_SDIO, FMC_SEN_LMK,FMC_B5, FMC_B6,FMC_DIR_CONTRONL).

WHAT should i do with those pins when i finishing my design?

  • Shuai,

    1. Yes, you can recompile the source code. Example code can be downloaded from the TSW14J10EVM product folder on the TI website. But you might be better off requesting free TI JESD204B IP source code that works with most Xilinx development boards. This code comes with example source code. You can request this IP by going to the following link:https://www.ti.com/tool/TI-JESD204-IP

    2. You would leave this signals floating. They are spares that are not used.

    Regards,

    Jim

  • JIM,

    In the TSW14J10EVM product folder source code,  I can edit the script " build_it.tcl" in txt, add my device information and run.(I wound try it in detail later.)

    The TI-JESD204 IP could be a better sollution, my request is under processing now.

    The other signals in FMC (named FMC_SCLK, FMC_SDIO, FMC_SEN_LMK,FMC_B5, FMC_B6,FMC_DIR_CONTRONL) links FPGA and CPLD on the EVM board through spi. In the User Guide I find I could decide which to use (FMC SPI or CPLD SPI) by choosing jumper J3.The default setting is CPLD.

    thanks for your kind  reply.

    Best regards,

    Shuai