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ADS42JB46: ADS42JB46 SPI logic level 1.8V or 3.3V?

Nan Li
Intellectual 260 points
Part Number: ADS42JB46

Hi everyone,

I have a question about the SPI control signals' logic level of ADS42JB46, 

1) I see that this AD part can support both 1.8V and 3.3V, so how can I choose the logic level as 1.8V or 3.3V?

2) what's more, I don't know why in datasheet, it shows 1.8V logic level only, because as I know, the 3.3V logic level is: Vil <= 0.7V, and Vih >= 2.0V.

Best Regards,

Nan

  • 0
    TI__Guru 66014 points

    Hi,

    The input pins are designed to be able to handle 3.3V IO based (larger signal). You do not have to do anything on your side. This is from the gate level design of the device. 

    The VIH and VIL threshold remain the same. This means you will need to find a 3.3V Buffer that can match the VOH and VOL of the input of the ADS42JB46

  • 0 in reply to Kang Hsia
    Intellectual 260 points

    Hi Kang,

    So what's the 1.8V logic level means in above figure? I don't understand your answer, which you mean ADS42JB46 can only support 3.3V level for the input ports,,,

    Regards,

    Nan

  • +1 in reply to Nan Li
    TI__Guru 66014 points

    Nan,

    The VIH and VIL of the input CMOS logic on the ADC remains the same, regardless of your output driver is 1.8V logic or 3.3V logic. 

    If you use 3.3V CMOS output driver to drive the input to the ADC, you will need to make sure you still meet VIH and VIL on the datasheet. 

  • 0 in reply to Kang Hsia
    Intellectual 260 points

    Hi Kang,

    Thanks very much, I have other 2 questions,,,

    1) so if the input ports support both 1.8 and 3.3V logic level, can it support 2.5V logic level?

    2) I find some FPGA board I/O ports which labels logic level "LVDS"(like KC705), but it also supports "Single-ended" I/O, how should I understand this point,,, when I use "Single-ended" mode, the logic level is LVDS or what?

    Regards,

    Nan

  • +1 in reply to Nan Li
    TI__Guru 66014 points

    Hi,

    1. regardless of your IO logic level, the ADS CMOS Input I/O VIH and VIL will not change. Yes, it will be 1.8V, 2.5V, and 3.3V IO logic tolerant. You will need to make sure the VIH and VIL threshold are met.

    2. This is the IO constraint file that you have to set in Vivado. You will need to check with Xilinx on this. TI cannot support this question.