Other Parts Discussed in Thread: LMK04228
Hi,
We would like some expert advice on the following: we are working on a design where we would connect
15 x ADC3693 to an Intel FPGA (Arria 10). At the FPGA-side the LVDS DDR data is handled by the ALTERA LVDS SERDES
component using an IOPLL instance (not much different than the TSW1400EVM). The IOPLL needs a dedicated clock
pin, however, of which we only have a couple.
So we want to share the clock input pin between multiple (i.e. 15) ALTERA LVDS SERDES IP blocks. Possibly also
sharing the IOPLL. If this is possible however is a question. We think that is dependent on the phase difference between the DCLK signals
of multiple ADC, which will all be clocked by the same DCLKIN (and sample clock).
Is the anything that can be said over the relation between the DCLK signal of multiple ADCs? Any other thoughts on this?
Thanks,
Rob van der Meer