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ADC3683: Possibility to share DCLK with multiple convertes

Part Number: ADC3683
Other Parts Discussed in Thread: TSW1400EVM, LMK04228

Hi,

We would like some expert advice on the following: we are working on a design where we would connect

15 x ADC3693 to an Intel FPGA (Arria 10). At the FPGA-side the LVDS DDR data is handled by the ALTERA LVDS SERDES

component using an IOPLL instance (not much different than the TSW1400EVM). The IOPLL needs a dedicated clock

pin, however, of which we only have a couple. 

So we want to share the clock input pin between multiple (i.e. 15) ALTERA LVDS SERDES IP blocks. Possibly also

sharing the IOPLL. If this is possible however is a question. We think that is dependent on the phase difference between the DCLK signals

of multiple ADC, which will all be clocked by the same DCLKIN (and sample clock).

Is the anything that can be said over the relation between the DCLK signal of multiple ADCs? Any other thoughts on this?

Thanks, 

Rob van der Meer

  • Hi Rob,

    If all ADCs are sharing a synchronous (same source) sample clock and DCLKIN, then the ADC outputs will be aligned/synchronous with one another. There may be some process variation in things like aperture delay, so some skew may be present across the ADCs outputs, but will be small enough (likely hundreds of pico seconds) to be absorbed by FPGA buffers, if needed.

    Since the DCLKIN signals are all coming from the same source (FPGA) to the ADCs, and these DCLKIN PLLs are locked to the ADC sample clock, I think that this approach should be fine since all of the clock will be frequency locked/coherent (phase is not critical since there is an internal DLL for DCLKIN, but is also synchronous in this case).

    It is also a possibility to use a clock distribution device for the DCLKIN signal (maybe a part like the LMK04228 which has 15 outputs). This may also be a good idea to use as a jitter cleaner since the FPGA jitter may not be all that great.

    Best Regards,

    Dan