DAC38J84EVM: DAC PLL out of lock

Shuai,

It appears you have either a bad serdes lane (#6) which could be due to an assignment error, or a timing issue with the FPGA (since you are seeing FIFO errors).  With the setup you are showing, the FPGA is receiving a 307.2MHz reference clock. Make sure this is what the firmware is expecting. If there is a possible issue with lane 6, try using the 4 lane approach shown in the attached file. You can also try the original 8 lane mode but with a reduced serdes rate to see if this helps. This mode is also shown in the attached file.

Regards,

Jim

DAC38J84_LMF_4421.pptx 

Dear jim

I've re-timing my program,making sure there is no timing issue in my program.
now the possible issue with lane 6 is no longer exist ,but the DAC pll is still out of lock,and the FIFO read error and FIFO Read Empty is still on.

What should I check now?(Sorry for those problems)

Thanks a lot

You are not using the DAC PLL so this is normal. I think the FPGA is having issues and you should contact Xilinx for help. If you use Chipscope, you should see the FPGA sending valid data after CGS has completed and the SYNC staying high. Double check the FPGA JESD parameters and make sure they are matching the DAC parameters. Is your FPGA expecting two clocks (core clock and reference clock) from the DAC EVM or one?

My test bench block diagram is above.
Input from DAC38J84EVM are:
sync0_p/n connecting  SYNCBP/N port (DAC),
refclk_p/n connecting  DCLKOUT0p/n port (LMK04828 , 307.2MHz),
sysref_p/n connecting SDCLKOUT1p/n port (LMK04828 , 307.2MHz)

data output to DAC are:
tx_p/n[7:0]. those are GTH transceiver, connecting according to the schematics.

I'm confused about those clocks.It seems that the frequency of refclk is set in the jesd204 ip, and sys_ref is 1/40 of line rate and set in the GUI.
I have tried ILA ,I found sometimes the sync_signal is low.

Is there any thing wrong?Or what should I do for further debugging?

Max SYSREF = data rate / (K * N) where N is any whole integer. In your setup, the max SYSREF can be is 61.44MHz. Give this a try.

Sorry,,but how to change the SYSREF individually?in my setup, the refclk and sysref comes from DCLKOUT0 and SDCLKOUT1. I think the refclk is 307.2MHz, and the sysref is also 307.2MHz because in the clock output page, the CLK0 & 1 are controlled by one divider.
In fact I'm not quite sure how to tune the frequency.

I have tried the 4421 configuration.seems the alarms still on.

What's the most likely problem, the program or the FPGA ,or any thing i should make sure of?

thanks

The FPGA.

SDCLK uses the SYSREF divider shown on the SYSREF and SYNC tab. You should have 160 for the default divider (see attached). This will create a SYSREF frequency of 15.36MHz which is fine for your setup.

4405.SYSREF.pptx

Shuai,

Here is an example project using the TI JESD IP.

Regards,

Jim

TI_JESD204_IP_KCU105_DAC38J84_841.zip 

jim

Thanks for your kind help.Now I will try to work on another FPGA board.

I want to program the FPGA as a DDS to be  the source of the DAC input data  (rather than simply reading data from the DDR),and using PC to fast tune the frequency and phase of the signal.Further, I hope to sum up several DDS digital signals to synthesize a new waveform.
The benefit is the data from PC are simplified into a few control commands.

I think the TSW14J56EVM would be a good starting point,there are 8 lanes and USB 3.0 port. Can I reprogram and modify the TSW14J56EVM to meet my demand? If it is possible, Can I  still use the TI-JESD204-IP or just modify the source code(is there enough logic gate source in FPGA to add my design?)? I'm a little worried about the difficulty to establish the jesd204b link between TSW14J56EVM and DAC 38j84.

wish to hear your Comments and suggestions.

Best regards,

shuai