ADS130E08: Serial clock frequency calculation

Hello Vineeth,

Welcome to Data Converters forums! I'm going to answer your questions out of order because it'll flow a bit better this way.

Question 2

I'd highly suggest you watch the TI Precision Labs video series on ADCs to develop your expertise. I took this slide from the basic operation mini-series (around 8:36): https://training.ti.com/ti-precision-labs-sar-delta-sigma-basic-operation 

As you can see, a delta sigma requires a main (formerly known as master) clock which can be external or internal, which is then stepped down to a modulator clock and then stepped down further to a data-rate. However, usually the data-rate is not a selectable parameter for the customer, but the OSR is, which can be calculated to understand data-rate.

This has nothing to do with the SCLK because the modulator works continuously on conversions and the SPI interface is used to actually grab the result of a conversion from the register. This should answer your 2nd question.

Question 3 and 4

At that point, you just need to hunt through the datasheet to find those values. I'll analyze the ADS130E08 datasheet as an example:

I want to first point out the text about a "fixed sample rate of 8kSPS" text. This is confusing but true if the internal oscillator is used to generate the main clock (f_CLK). If I were to change the text, I would explicitly call out that the OSR and modulator clock (f_MOD) scaling is constant within the device and a user would have to change to external clock mode if they would like to change from the 8kSPS sample rate.

This explains why the internal oscillator frequency expect f_CLK (or main clock) to be 2.048MHz instead of a range of values. Using the rest of the information, we learn that f_MOD (or modulator clock) is 256kHz (or 2.048MHz/8). With that, we can find the OSR to be 32 (or 256k/8k).

So, if I wanted 3kSPS, I'll need f_MOD of 96kHz (or 32*3k) which results in f_CLK of 768kHz. I'll let you calculate what you need for 5kSPS

Compared to the ADS131E08 you can tell the input clock range is much wider, and there is an OSR register bit, so you'd keep a constant f_CLK and change the OSR to quickly change between different sampling rates.

Question 1

Finally, I would say we have two constraints on what SCLK should be. The first constraint is that it cannot be faster than 20MHz (1/50ns). This is outlined in the Electrical Characteristics section.

The other constraint is that we need to clock out all the data before next conversion finishes. The datasheet has a good paragraph on it here:

If you'd like my advice, I would look into ADS131E08 has a direct replacement for the ADS130E08. The ADS131E08 is better documented, and doesn't have strange data formatting issues. ADS130E08 was really intended to be simple and designed with specifically 8kSPS in mind. If you don't mind more complexity but more flexibility, ADS131E08 is much better.

Best,

-Cole