The ADC12DJEVM is attached to a Xilinx XCVU13P using the JESDC core 4.2 from Xilinx. I am getting the link up correctly, but the upper 4 lanes are not receiving the ramp pattern that I see on the lower 4 lanes; or more specifically, the upper 128 bits from the JESD core streaming interface are incorrect when compared to the lower. I am getting link up, with sync and the Xilinx core reports a captured sysref (JESD204B, Subclass 1). I am running the ADC in JMODE2. I am not seeing any frame errors after the ILA sequence, I can transmit K28.5 symbols on all lanes. I have checked the JESD link parameters in the Xilinx core to confirm they match the ADC spec. Any reason that the upper bits of the streaming interface are invalid in this mode?
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