TSW54J60EVM: Spike noises in the ADC data

Hi Yuke,

Are you able to get the TSW54J60 EVM working with our data capture board?

The issue is not the ground connections, unless the EVM is not fully seated in the Xilinx FPGA dev kit that is being used.

Also, tying the analog inputs together at the SMAs, might not be helpful. I would disconnect/unsolder the output AC coupling capacitors after the amplifier and tie those two nodes to each other and ground.

Regards,

Rob

Yuke,

Attached is what you should expect to see with an input and with no input on the TSW54J60EVM. This was captured with the TI TSW14J56EVM. What is the gain setting you have for the adjustable amplifier? If this is set properly, it appears your issue may be with your firmware.

Regards,

Jim

TSW54J60.pptx

Rob,

Thanks for the response. Glad to know that we can use the demo board for formal product. 

I am still not sure which output AC coupling capacitors you are referring to ?  Do you mean C9 and C23 ?

-Yuke

Jim,

Many thanks for the suggestions. I set the gain of the Chan B to 0dB (LMH6401). When I put a 10MHz 100mV sine wave signal to INBP/J3 and leave INBN/J4 open, I get relative OK sine waveform.  I don't see any issues in the firmware. Any suggestions ? Sorry we didn't purchase the TSW14J56EVM board to test the data. Any suggestions on how to reduce the noise ?

Thanks,

Yuke

Yuke,

Is there a chance the samples are out of alignment in the FPGA? I would try sending a sawtooth waveform for an input or a lower frequency sinewave to see if you can observe this with the raw data. Have you tried a different power supply? 

Make sure to reset the ADC after the LMK has been configured. What configuration files are you using?

Regards,

Jim  

Hi Jim,

I do have the word order issue when the FPGA receives the ADC data. The 8 words in each channel (I am using 8224 LMFS mode) are often out of order. I have to use a sine waveform input to find the correct word order. Otherwise I got the "Saw" pattern in a smooth sine waveform input. Fortunately I only need to do this "word order calibration" once when JESD communication is established.  I don't know the root cause.  Is there  a way for me to use the "Long Transport Layer Test Pattern" or "12 Oct RPAT" data to test the word order ?  If I know the correct word order in the test pattern data, I don't need to feed a sine waveform every time I establish the JESD communication.  Fig.1 is the LabView page for the test pattern.  Fig.2 is the data I got (already changed to floating point) for the "Long Transport Layer Test pattern" and Fig.3 is the "12 Oct RPAT" data. I don't know how to explain them and use these test data to figure out the word order. 

Besides the word order issue, I think the spike noise is a different issue. If the words are out of order, I shouldn't get spikes when there is no input or shorted inputs. Is that right  ? Attached is the config file I am using. I combine the TI-provided PLL and ADC config file. I did follow the instructions to do the digital reset, then analog core reset, and then send one SysRef pulse. 

I appreciate your help on the spikes issue and the ADC word order issue.

ThanksADC_Config_All.cfg

Yuke

Fig 1. ADC board JESD setting 1

Fig. 1 ADC board JESD setting

Fig. 2  Floating format data when select "EN Long Transport Layer Test Pattern" Can I use this to find the correct word order ?

Fig. 3 Floating format data when select "12 Octet RPAT" test data. Can I use this to find the correct word order ?

Yuke,

I would suggest using the long transport pattern by setting bit 4 in address 0x00 of page 0x6900.

You can also try a ramp pattern that is not in the data sheet by following the attached document. Since this part has 4 interleaving ADC's, the ramp created by each ADC are not synchronized so the pattern is not a perfect ramp. This is why it was not included in the data sheet. Not sure if this pattern will help you or not.

Regards,

Jim

ADS54J60_test_pattern_ramp_mode.pptx

Jim,

Thank you for the suggestion.  I finally found my issue on the word sequence: if I turn on the "Frame_ALGN", bit[1] of register 0x690000, the word received on the Xilinx JESD204 core will have the same order as the ADC datasheet.  

The only remaining question is the spike noise. With the correct word order, we still get some spikes in the data (the peak to peak count is about 200 LSB of the 16-bit ADC).  I don't know where it is from. The only guess is the one shared common ground of analog ground and digital ground.  

From your note, it seems the peak to peak is about 88 count. For a 16-bit ADC, does this mean we lose quite a few bits ?  Is there any way to improve this ?  For example, redesign our PCB by separating digital and analog ground plane ? Of course, our data is even worse (200 peak to peak count). 

Thanks a lot for helping us to make the most use of this ADC chip.

-Yuke