Other Parts Discussed in Thread: ADS54J60, , LMH6401
Hello,
We are using TSW54J60EVM (ADC chip: ADS54J60) with a Xilinx FPGA to build a high speed data acquisition system. So far, we got the ADC and data communication (JESD204B) working. Thanks for the support in this forum. Thanks Jim.
Now we have an analog related issue. Somehow we got some strong spike noises in the ADC data. Attached (Fig. 1) is a screen shot of the noises (we normalized the max reading to +/- 1.0). The noises (+/- 0.008 and +/-0.004) count about 260 counts (it is a 8bit lost !). This noise in the same (amplitude and spike characters) if we leave the input SMA open, or if we short them +/- together. This is also the same for Channel A and Channel B. We spent a lot of time to check the sources of the noises. Does anyone has any suggestions ? The following are our puzzles:
1) We think this noise is from the digital circuit. On the TSW54J60EVM board PCB layout, it seems the digital ground and analog ground are using the same PCB layer. On the ADC datasheet (Fig. 2), it says "GND=AGND and DGND connected in the PCB layout". How to avoid digital ground noises affect the ADC data ?
2) The second digital noises could be from the FPGA GND signals on the FMC. These FPGA GND signals are on the FMC pins. How to prevent these noises going to the ADC data ?
3) Since we are using the TSW54J60EVM with our Xilinx FPGA board, we didn't purchase the TSW15J56EVM as shown in the TSW54J60EVM datasheet (Fig.3). Does anyone using the TSW54J60EVM demo board and got a true 16-bit resolution in the ADC raw data ?
We are eager to solve this noise problem and use the chip with the full resolution. Please help us. Thanks a lot !
-Yuke
Fig.1 ADC noises with inputs on SMA open or shorted together
Fig.2 Datasheet of ADC chip show AGND and DGND connected in the PCB layout
Fig.3 Setup suggested from TI