ADC12DJ3200EVM: JESD204B Rx lane buffer overflow issue

Hi Rohit,

I am not sure about the architecture of the JESD IP that you are using, but one condition the buffer overflow will occur if the core (application data) side clock is not derived from the same root clock that is driving the reference clock to the FPGA transceiver.

The other possibility is that you have configured the JESD IP to have all lanes across both ADCs to release together, and the ADCs are not aligned using SYSREF. In that case, the ADC whose multi-frame event is lagging will force the other ADC's lanes to buffer extra data. There is a possibility that this can cause buffer overflow.

Regards,

Ameet

Hi Ameet

Thanks for the response.

My JESD clock is derived by same root clock that is driving the reference clock of the FPGA transceiver.

I am using JMODE2 mode (sub- class 0) with 4 lane configuration. In our JESD Rx IP, once the first octet of the ILA sequence is detected on a lane, the data gets buffered and remain held in the buffer until all lanes detect first octet of their ILA sequence. When all the lanes detect their first octet, the buffers release this data at the same time. We do have RX controller block which performs re-initialization of lanes in case any lanes fail to detect the ILA sequence.  ALIGNED signal is asserted once the lanes are properly aligned.

Though, I don't have SYSREF (as I use sub class 0) to align the ADC lanes but our JESD Rx takes care of the lagging if lanes are out of sync from ADC. What do you think?

Regards

Rohit

Hi Rohit,

It seems like you are connecting two ADCs to a single Rx IP in the FPGA. May I know the K value programmed in the ADC and the depth of the FPGA IP’s elastic buffers?

If you aren’t synchronizing the ADCs using SYSREF, it may be easier to use a separate Rx IP per ADC. Or you will need to have buffers that are deep enough to hold a multiframe of data.

Regards,

Ameet

Hi Ameet

I think there is some confusion, I am using two ADCs (because of JMODE2) but since my Rx IP is configured for only 4 lanes hence I am only using one JESD Block (one link, 4 lanes) to send data to my 4 lanes Rx IP. Analog signal is only provided to single channel. Hope this is clear or let me know if I am missing anything here .

K value programmed in ADC is 4. The Rx IP is configured with same L,M,N12,F, K value as given in Table 19 of ADC datasheet.

Regards

Rohit