This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS1226: Unexpected convertion and autocalibration times

Part Number: ADS1226

Hello,

We have an issue with random conversion and autocalibration times after startup.

In our design, we have a recovery mechanism that powers down the device for short duration (can be betweeen 200ms and 600ms).

The sequence is as follows:

1- Normal function: we are currently in a loop with a calibration time of ~300ms, which is expected

2- Power down of ~200ms to ~600ms of AVDD and DVDD. Please note that DVDD may not quite get down to 0V.

3- Power up of AVDD and DVDD with all ADS1226 inputs set to low state (including Start pin)

4- After 5ms, our FPGA is in high impedance mode so all inputs are set to high state (including Start pin)

5- After another 10ms our FPGA is set up and drives the start pin low with standard operation (calibration + conversion loop on 2 channels)

=> Depending on the power down duration, we observe a calibration time between 80ms and 600ms. This time stays always the same if we do not power down the device.

Also we observe that:

- when we have a longer power off duration (>2s), we have no issues (~300ms).

- when we have a very short power off duration (~200ms), the calibration time is exactly the same as just before (correct or incorrect).

A/ What we need to know is how the internal ADS1226 clock is settled.

B/ Depending on this clock is there a maximum for the conversion/calibration time ? Can it be above 10s for example?

C/ When these times are not inside nominal boundaries, is the conversion of acquired signal still accurate?

Thank you

Kind regards.

  • Hi Pierre,

    Most likely what you are seeing is an issue due to an incomplete POR.  From a cold start (supplies completely collapsed) to a powered on state, the device will be held in a reset condition until the supplies are at a threshold where the ADS1226 can operate in an expected way.  With some of our older devices the POR circuit is basically a series resistor and a cap.  When the cap is charged to a certain level the device is released from the reset state.  The problem with this circuit is there is no easy way to discharge the cap except back through the large value of resistance.  If the off time is long enough this doesn't present an issue.  However, if the power is switched quickly on-off-on, the device may not properly reset and the device may not come back to a known operating state.

    Unfortunately I cannot give you a precise discharge time as it will depend on many factors in your system to include cap loading and any additional charge from inputs that may still reside within the IC.

    For A) in normal operation following the release from the reset state, there is an internal counter that counts up until the internal clock is settled.  The value is determined by the designer and will differ in time slightly from device to device and lot to lot variation.

    For B) we don't have data for when the device is not operating in the correct state.  Our validation testing is always from a cold start condition.

    For C) again it is difficult to say how the device is working when in an unknown operating state.  Most likely it will not be operating as expected.

    The best advice I can give you is to hold the device in a completely off (no power supplied) state long enough for the device to respond correctly when once again powered up.  I did do some testing on a different device that had a similar POR circuit and it took a minimum of 1.5 seconds for the device to power up correctly.  So 2 seconds in your system may not be far off.

    Best regards,

    Bob B