Hello,
We have an issue with random conversion and autocalibration times after startup.
In our design, we have a recovery mechanism that powers down the device for short duration (can be betweeen 200ms and 600ms).
The sequence is as follows:
1- Normal function: we are currently in a loop with a calibration time of ~300ms, which is expected
2- Power down of ~200ms to ~600ms of AVDD and DVDD. Please note that DVDD may not quite get down to 0V.
3- Power up of AVDD and DVDD with all ADS1226 inputs set to low state (including Start pin)
4- After 5ms, our FPGA is in high impedance mode so all inputs are set to high state (including Start pin)
5- After another 10ms our FPGA is set up and drives the start pin low with standard operation (calibration + conversion loop on 2 channels)
=> Depending on the power down duration, we observe a calibration time between 80ms and 600ms. This time stays always the same if we do not power down the device.
Also we observe that:
- when we have a longer power off duration (>2s), we have no issues (~300ms).
- when we have a very short power off duration (~200ms), the calibration time is exactly the same as just before (correct or incorrect).
A/ What we need to know is how the internal ADS1226 clock is settled.
B/ Depending on this clock is there a maximum for the conversion/calibration time ? Can it be above 10s for example?
C/ When these times are not inside nominal boundaries, is the conversion of acquired signal still accurate?
Thank you
Kind regards.