Hello,
I will be driving the DAC3154 from a Xilinx Series 7 FPGA (using the OSERDESE2) and wish to use the single 10 bit bus to multiplex data for both A and B DACS on the chip.
In this situation the output SERDES from the FPGA can drive the DDR output bus only with the clock edge aligned, and not center aligned (the default norm for the DAC).
Assuming that the clock / data skew from the FPGA is minimal, could you please recommend a setting for config3 (datadly, clkdly) that might work best here.
Thank you,
David
