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ADC12D1600: some questions about ADC12D1600

Jiahui Gao
Intellectual 1650 points
Part Number: ADC12D1600

Hello,

I have the following five questions about ADC12D1600 chip:

a) The chip includes demux and non demux modes. Is there a fixed phase relationship between DI and DID in demux mode? Or is it just a simple sampling sequence?

b) According to what do designers choose demux and non demux modes?

c) Are there any other differences between demux and non demux modes except that the data port rate and the number of output data bits are different when outputting data?

d) Is the analog signal input I and Q related to the traditional IQ data stream (phase difference of 90 °), or are they just two groups of completely unrelated signals?

e) As for the DCLK clock, can the output at 1 / 4 sampling rate under demux mode be understood as: if the total sampling rate is 1.6gsps under non-DES and demux modes, the DCLK is 400msps?

Looking forward to your reply！Thanks！

  • 0
    TI__Mastermind 25260 points

    Hi Jiahui,

    See my comments below.

    Regards,

    Rob

    a) The chip includes demux and non demux modes. Is there a fixed phase relationship between DI and DID in demux mode? Or is it just a simple sampling sequence? RR: just a simple sampling sequence. I would study figure 3 to use this mode.

    b) According to what do designers choose demux and non demux modes? RR: Really depends on the application and what the capabilities/resources are available for capturing the ADC's data. If the 1:2 Demux Mode is selected, the output data rate is reduced to half the input sample rate on each bus. When Non-Demux Mode is selected, the output data rate on each channel is at the same rate as the input sample clock and only one 12-bit bus per channel is active.

    c) Are there any other differences between demux and non demux modes except that the data port rate and the number of output data bits are different when outputting data? RR: no, not really, see my answer on question b.

    d) Is the analog signal input I and Q related to the traditional IQ data stream (phase difference of 90 °), or are they just two groups of completely unrelated signals? RR: I and Q refer to channel A and channel B. No phase relationship in the signals.

    e) As for the DCLK clock, can the output at 1 / 4 sampling rate under demux mode be understood as: if the total sampling rate is 1.6gsps under non-DES and demux modes, the DCLK is 400msps? RR: yes, correct. 

  • 0
    TI__Intellectual 1650 points

    Hi Rob,

    I'm glad to receive your reply.

    However I have two more questions to ask you.

    a)When channel A and channel B are respectively processed internally by ADC, are the signals of each channel converted into I/Q data stream (90° phase difference) for processing?
    b)Is FPBW equivalent to the input frequency range?

    Regards,

    Jiahui

  • 0 in reply to Jiahui Gao
    TI__Mastermind 25260 points

    Hi Jiahui,

    See my comments below:

    a)When channel A and channel B are respectively processed internally by ADC, are the signals of each channel converted into I/Q data stream (90° phase difference) for processing?  RR: The I/Q signal are not processed with a 90deg phase difference, they are both processed at 0deg phase offset from each other, if you use the ADC in dual channel mode. Otherwise, the channel phase offset is 180deg phase difference when using this device in its interleaving mode or DES mode.
    b)Is FPBW equivalent to the input frequency range? RR: yes, you can use input frequencies near the FPBW edge, however, the converter will start to degrade in AC performance, ie - SNR, SFDR, etc, the higher the input frequency.
    Regards,
    Rob