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# ADS1298: Maximum Speed of the SPI

Hi Team, related to this post.

We trying to understand the equation in the discussion
Basically the clock for serial digital output is constrained by t_SCLK < (t_DR - t_CLK) / (N_BITS * N_CHANNELS + 24), where t_DR is the sampling period, t_SCLK is the digital output clock period, and t_CLK is clock period which is very small and can be ignored.

According to datasheet, the minimal t_SCLK is 50ns. This means the sampling period has to be larger than 50ns * (24 * 8 + 24) = 0.108us (assuming 8 channels and 24 bits). So the maximum sampling frequency is about 93 ksps, which is quite different from the 25.6ksps claimed in the datasheet.

We trying to figure out if 25.6ksps is for a single channel or for the overall 8 channels. If it's for a single channel, the numbers don't add up as shown.

Thank you.

-Mark

• Hello Mark,

The device champion is out of office for the holidays and will be back on Jan 3. He will get back to you during that week.

• Hi Mark,

Thanks for the support.

Equations 6 and 7 in the datasheet can be applied for different numbers of channels and numbers of bits. For example, for the minimal t_SCLK of 50ns with 24-bit data and 8-channels, the maximum data rate is approximately 93ksps (10.8us ). Can you please clarify or show how you get the 25.6ksps as claimed in the datasheet?

Thanks

-TC

• Hi TC, sorry for the follow-up response.

it's actually 32ksps. On p.3, in the 2nd paragraph of "Description" section, "The ADS129x and ADS129xR operate at data rates as high as 32 kSPS".

• Hi Mark,

Thanks for the clarification.

Yes, the maximum data rate of the ADS129x and ADS129xR is 32 kSPS. The calculation for Equation 7 shows the minimum speed required for SCLK depending on the number of channels, number of bits of resolution, and the device's output data rate. It is not to be confused with the device operating data rate.

Thanks

-TC