**Part Number:**ADS1298

Hi Team, related to this post.

We trying to understand the equation in the discussion

Basically the clock for serial digital output is constrained by t_SCLK < (t_DR - t_CLK) / (N_BITS * N_CHANNELS + 24), where t_DR is the sampling period, t_SCLK is the digital output clock period, and t_CLK is clock period which is very small and can be ignored.

According to datasheet, the minimal t_SCLK is 50ns. This means the sampling period has to be larger than 50ns * (24 * 8 + 24) = 0.108us (assuming 8 channels and 24 bits). So the maximum sampling frequency is about 93 ksps, which is quite different from the 25.6ksps claimed in the datasheet.

We trying to figure out if 25.6ksps is for a single channel or for the overall 8 channels. If it's for a single channel, the numbers don't add up as shown.

Thank you.

-Mark