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ADC3683: Bit 17 high with test pattern 0 (or any other)

Part Number: ADC3683


Something small I do not fully comprehend: when I enter 'Custom pattern' and pattern value 0, I see in the HDSC application

that bit 17 is high -> 131072. When 131072 is entered as a test pattern the output is truly 0. As we are attempting to

use the custom pattern to align data (and omit FCLK) we would like to understand the exact relation between

the value in test pattern and the output value. Can you elaborate? (The datasheet suggests a 1:1 relation)

Thanks again for your adequate and fast support!

Regards, Rob van der Meer

  • Hi Rob,

    Since the data output format is defaulted to 2's complement, I believe that you may be seeing bit 17 as a "1" (or 131072 codes) due to this.

    Can you please set registers 0x8F and 0x92 to 0x02, and see if this sets this bit 17 to 0 when using the custom pattern?

    Best Regards,


  • Thanks, that has indeed the intended effect. I was assuming this register only had an effect when decimation is enabled, but it applied to the custom pattern also.