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ADS9110: Connect CS and CONVST together generating problems?

Marcel Kummer
Prodigy 10 points
Part Number: ADS9110

Hallo everyone,

I need to interface the ADS9110. Our hardware developer wired the ADC like described in chapter 7.5.4.2. (Single Device: Minimum Pins for a Standard SPI Interface)

But when reading the chapter 7.5.2 (Interleaving Conversion Cycles and Data Transfer Frames) it's stated that:
"To achieve the rated performance specifications, the host controller must ensure that no digital signals toggle
during the quiet acquisition time (tqt_acq) and quiet aperture time (td_cnvcap) [...]"
Furthermore all timing-diagramms in this chapter show, that the CS goes low after td_cnvcap.

Isn't the connection between CS and CONVST breaking this rule?
What are the consequences regarding performance, when connecting CS and CONVST?

Thanks and regards,

Marcel.

  • +1
    TI__Mastermind 43550 points

    Hi Marcel,

    Welcome to the TI E2E Community!

    You can connect CS and CONVST pins together and still meet the requirements of the ADC.  When CONVST goes high, this starts the conversion cycle.  Taking CS high transitions the SDO pins from active to hi-z and will not cause any degradation in noise.  The key concern is not to drive the SCLK pin during these periods, which can couple noise into the input, especially when CS is low and the SDO pins are also actively toggling.

    I see how the use of the term 'no digital signals toggle' seems to preclude this use case, but as long as these pins transition low to high at the same time, you will not degrade the performance.  Also, the minimum high time for CONVST is 30nsec, which automatically meets the td_cnvcap quiet time of 10nsec.

    If you violate these quiet time periods, you can expect the SNR and ENOB to decrease, but by how much is hard to predict, as it would depend on the capacitive loading on the pins due to board layout, digital supply voltage, and so forth.

    Regards,
    Keith Nicholas
    Precision ADC Applications

  • 0 in reply to Keith Nicholas
    Prodigy 10 points

    Thanks, that made it clear.

    I have one more question about this topic. When CS and CONVST are connected, the data I will read is allways the adc-value measured at the time of the previous data read, is this correct?

    This means if I read the data every second, the read value is one second old?

    Thanks and regards,

    Marcel.

  • +1 in reply to Marcel Kummer
    TI__Mastermind 43550 points

    Hi Marcel,

    It depends if you transfer data in Zone 1 or Zone 2, as defined in Figures 47 and 48.

    For Zone 1 transfer, the data retrieved is the conversion result for the same frame.  (Frame 1 conversion result retrieved in Frame 1)  In Zone 2, the data retrieved is the conversion result of the previous frame.  (Frame 1 conversion result retrieved in Frame 2)

    In order to use Zone 1 transfer, you would start the conversion with the rising edge of CONVST:CS and hold high for the maximum conversion time, t-conv-max=670nsec.  You would then take CONVST:CS low and clock the conversion result out of the device.  In this case, the data is less than 1 second 'old'.

    If using Zone 2, then you are correct, the data that you read is from the previous frame and will be more than 1 second 'old', but less than 2 seconds depending on how fast you retrieve the data.

    Zone 2 is useful to provide more time to retrieve data, lowering the SCLK speed needed.  However, when running at lower data rates (such as 1sps), it is more convenient to use Zone 1 since you have plenty of time to clock the conversion result out of the device.  It also reduces the response time to less than 1 data rate period, or in this example, less than 1 second.

    As an example, if using an SCLK frequency of 10MHz, then you can use Zone 1 transfer over a single SDO line for data rates less than 370ksps.

    Regards,
    Keith