ADC3422: Clock selection of ADC3422

Hi Xiaoqiang,

Option 1 will have better performance - clock inputs that are driven differentially have reduced susceptibility to common-mode noise.

The key here is the board layout. To reduce noise generated from the power supply, be sure to keep the analog and digital power supplies separate.

Regards, Amy

Hi Xiaoqiang,

The ADC clock inputs should be AC coupled, so the logic voltage (2.5/3.3V) shouldn't matter all that much as long as the differential voltage swing is sufficient. Since it is LVDS, I would expect a ~700 mVpp differential voltage which is fine. The LVDS common mode voltage will be blocked by the AC coupling caps.

Best,

Dan

Hi Xiaoqiang,

No conflict in this answer. LVDS is actually 320mVpp differential not 700mVpp.

Regards,

Rob

Hi Xiaoqiang,

I apologize for the confusion.

There are really two questions here....

The recommendation would be to use an LVDS clock or oscillator because it has better common mode noise reduction and the ADC would prefer to have a differential clock interface.

However, the better solution is to think of an ADCs clock as part of the analog circuit. So using a clock or oscillator with an analog supply is the better choice. This will minimize the noise impact that could be generated from the digital supply to couple into the clock and therefore, degrade ADC performance.

Regards,

Rob