DAC38J84EVM: DC Coupled Sysref

Hi Kang,

Thanks for your response.

I have one more question.

FPGA is continuously sending BC's and DAC is not making the sync_p signal low.

What might be the issue ?

Pavan,

Make sure you are following the steps in the attached document.

Regards,

Jim

4604.DAC38J84 Start-up Sequence.docx 

Hi Jim

I am using DAC38J84 with my Custom FPGA Board (Which contains some third Party FPGA).

I have attached my DAC configurations . JESD Linkup is working with these configurations

4863.DAC_config.cfg

What I have found is My DAC is working only with K = 32 and RBD > 20.

It is not working with K= 16 and Any RBD ?

What does this means ?

Does this means that, there is lot of skew in the FPGA to DAC Chip path ?

Is my understanding correct ?

Paven,

It appears your F value is 1. Per the JESD204B standard, 17 < K*F < 1023. You must use a K value larger than 16 with F = 1. I would suggest trying 20.

Regards,

Jim 

Hi Jim

I think I have shared the wrong configuration file. Sorry for that

DAC.cfg

L = 4

K = 32

F = 2

 So Ideally, K*F > 17 => K can be above 10. So with K = 10 also my configurations must work ?

Then your issue is probably to much lane skew. How does the system work with K = 20?

Hi Jim,

The problem is not with the values of K.

Even at K =32, my sync is toggling

But Sync signal is low for 1 Clock cycle and high again

There are no Errors in the DAC

Suppose if sync is low....it must wait till we send BC characters, but here as soon as it gets low again it is high.

So My IP is continuously sending CGS and ILA data

I am using CMOS_SYNC_AB.

Does the J21 chip create any problem ?

Hi Jim,

The problem is not with the values of K.

Even at K =32, my sync is toggling

But Sync signal is low for 1 Clock cycle and high again

There are no Errors in the DAC

Suppose if sync is low....it must wait till we send BC characters, but here as soon as it gets low again it is high.

So My IP is continuously sending CGS and ILA data

I am using CMOS_SYNC_AB.

Does the J21 chip create any problem ? 

I think the problem is in the Sync path between FPGA and DAC .

What is the frequency of SYSREF? The max value with K = 32 is 9.6MHz. Please send screen shots of all of the LMK and DAC settings. Maybe you have something set wrong.

Hi Jim

1. K =32

2. F =2

3. Sysref Freq = 9.6 MHz

dac_x8 - config.cfg

After all these configurations are done, I am resetting the DAC JESD Core

Issue : 

I am using Sync_ab .

Sync_ab is going low for one clock cycle and becoming high immediately

FPGA Clock = 153.6 MHz and K = 32, F = 2

Please check my configurations

Pavan,

I do not see the 0xBCBC characters in the screen shot above. I ran your setup with no issues using our pattern generator board. The config file is attached. What does the alarm tab show you when you click on clear and read alarms? Do you have any way of using the LVDS SYNC?

Regards,

Jim

 4421_K_32_Fs_2457p6.cfg

What do you mean by this comment you made earlier?

In the Datasheet, it is mentioned that Clock and Sysref Standard is LVPECL (AC Coupled).

But in the EVM Schematics, Sysref  is DC Coupled . So recommended Standard is LCPECL .

Now by mistake, I have connected LVPECL16 from LMK04828 to DAC. Does this damage the sysref path ?

Did you add some wires to the board? This makes no sense.

Jim,

No, I did not add wires.

I have changed the standard to LCPECL.

I have verified the sysref and clock path by resetting NCO through Sysref.

So there is no issue with LCPECL standard of Sysref

Jim

1. Blue Line indicated the trigger position

2. In the Alarm tab, there are no errors. Everything is good.

3. Yes I can try with LVDS Sync.

Also if by any chance....Sync goes low, it must be low until it detects BC characters again. But here sync is low only for 1 clock cycle 

Pavan,

The SYNC will toggle low once the DAC is configured. This is normal. After this, and when the FPGA is ready to send BCBC data, after doing the DAC initialization step (click "Reset DAC JESD Core" on the GUI, then selecting "Trigger LMK04828 SYSREF", the SYNC will go low then high after receiving the BCBC characters.

Regards,

Jim

Hi Jim

Sync Toggling issue is resolved. The Problem is in the FPGA Firmware.

We are not sending proper ILA data after sync is High.

Thanks for your support.

Now at x8 interpolation, my JESD Link is working, but at x1 it is not working.

FPGA code will be same for x1 and x8  right ? 

FPGA Clock = 153.6 MHz

FPGA Sysref = 9.6 MHz

DAC Clk = 307.2 MHz

DAC Sysref = 9.6 MHz

Configurations for x1 are attached.

Please verify them.

4421_K_32_Fs_312p5.cfg

Also can you explain the operation of Multiplier and VRange

Line Rate = SERDES CLK * Multiplier * 2?

(2 is beacuse of the Half Rate)?

Jim,

Can you explain the Multiplier Register which I have pointed out in the previous post.

So I can make configurations at other Interpolation factors also.

Line Rate = SERDES CLK * Multiplier * 2?

(2 is beacuse of the Half Rate)?

Try other values for RBD.