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ADS42LB49: DDR mode LVDS data question

jung fang
Prodigy 80 points
Part Number: ADS42LB49

hi,

in my dsign. ADS42lb49 works in DDR mode, and LVDS data signal has some problem when sampling a 200mv square signal. as ADS42lb49  input Vpp max is 2V, so when 200mv signal input to INAP/M, DA12P/M should keep 0, but i captured alternative 0/1 signal in DA12P/M. i forgot to store waveform, will upload later.

firstly, let me introduce some test condition.

1/ADS42lb49 LVDS output clock/data  signal connected to FPGA and fpga internal 100ohm termination is enable.

2/power is ok, AVDD3.3,AVDD1.8,DVDD1.8 all  ok.

3/ads42lb49 input clock  is AC coupled and has 100ohm termination close to ads42lb49. input clock differential swing is 800mv and 200Mhz.

4/no signal input to analog portA&B 

5/SPI setting as follows, and SPI write/read is ok.

0x08  0x01//reset firstly

0x08 0x08//disable CTRL1/2 power down control

0x15 0x01//DDR mode

0x20 0x01//disable CTRL1/2 power down control

0x0f 0x44//run digital ramp test  pattern. below is channel A DA0P(pin 42) waveform ,so ADS42lb49's digital block to data output is ok. 

when sample analog input signal, all setting are same except sett 0x0f to 0x00.

BTW, analog signal input to INAP/M is same as follows but DC coupled, and INP common mode voltage is 1.9V, INM is 1.85V. i don't know whether DC couple will cause some problem.

another question is pin29/30, External sync input. If not used, connect SYNCINP to GND and SYNCINM to AVDD. are pin29/30 should connected to GND/AVDD directly or through a pull up/down resistor.

and can you share EVM schematic here. thanks!

 

  • 0
    TI__Guru* 91947 points

    Jung,

    If SYNC is not used, you can tie SYNCINP directly to GND and SYNCINM directly to AVDD.

    By default, the part data format is 2's comp. I would expect the MSB (DA12) to toggle with a low amplitude input if it was AC coupled. Change the data format to offset binary if you do not want this bit to toggle wit this input.

    You mention the analog input is DC coupled but you are showing AC coupling in the schematic. How is the input configured?

    The signal in the waveform above (DA0P) does not look correct if using the ramp test pattern. Are the data lines terminated properly by the FPGA used to capture the data? Are the P and N traces matched length? 

    Regards,

    Jim