I'm not sure how to drive the ~SYNC interface on the ADC32J42. The datasheet does not give a differential voltage spec.; only a VHI, VLO, and VCM.
The eval board statement "Provide LDVS to LVPECL DC Coupled translation" is a bit confusing: the board terminates each leg of ~SYNC at 50 ohms to 0.95V, which not appropriate for DC coupling of either noted standard.
I am planning to interface directly to a Xilinx Zynq-7000 series SoC. I have LVDS-compatible I/Os available: VCM is 1.25V (typ) and the differential output voltage is 350 mV (typ - so a logic high is +350 mV, logic low is -350 mV). See table 15, page 14 of the attached datasheet (ds191*.pdf).
I'll note that this question has been lingering on the e2e forum for six years without a clear resolution. The posts below indicate that LVDS drive should be OK, but TI has not published an updated datasheet or any definitive guidance.
ADC32J42 Datasheet:
ADC32J42 Eval Board:
