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ADC16V130: Timing

Genius 16019 points
Part Number: ADC16V130

Hello Experts,

We have this query from client:

We want to change the input clock of the ADC dynamically in my design, so that after a number of clocks the device samples with the new frequency. During the frequency change (~ 75 mS) the input clock of the ADC is stopped. Questions are:

1. Can we stop the input clock for this time ?
2. Are offering the new clock to the ADC, do we have to wait for some clock cycles or can I use immediately the output data ?

 

In the table above the minimum input frequency is 1 MHz.

 In the text above TI doesn't recommend  the input frequency below 5 MHz.

These two statements seem contradict with each other. Question is:
3. What minimum frequency shall I use for my design ?

Thank you.

Regards,
Archie A.

  • Hi,

    Using a clock down to 1MSPS is fine with this part. The text, just denotes that an clock below 5MSPS the duty cycle stabilizer won't be realizable, because with this low frequency clock signal, the feedback loop is not stable internal to the ADC.

    You can also stop the clock to the ADC at anytime. Keep in mind that when you re-start the clock, the ADC's output data won't be valid until after11 clock cycles to clear the pipeline latency.

    Regards,

    Rob