The TI E2E™ design support forums will undergo maintenance from Sept. 28 to Oct. 2. If you need design support during this time, contact your TI representative or open a new support request with our customer support center.

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DAC38J84: errors in the DAC outputs

Part Number: DAC38J84

Hello Team,

My customer is using the DAC38J84IAAV and am seeing, on occasion, errors in the DAC outputs. They are using DACA and DACD, not DACB or DACC (they have grounded the outputs of DACB and DACC).  (1) Is it a problem if DACB and DACC are not in sleep mode whilst their outputs are grounded? (2)they inadvertently driving RESETB high with 3.3V - would this cause a problem? (3) Is RESETB level or edge triggered? Any assistance would be much appreciated?

Regards,
Renan

  • Hi Renan,

    Could you please advise if your customer can read back the alarm registers to see if there are any errors in the JESD204 link or DAC circuits in general?

    to answer your question:

    1. no, DACB and DACC do not need to be in sleep mode with the output grounded

    2. it is a reliability problem and the DAC may fail earlier than usual. It may still be functional but TI cannot ensure its long term reliability.

    3. RESETB is level triggered.

  • Hello Kang,

    Apologies for this reply. Please see the response form my customer

    Basically we are able to read the registers and get the following:
    Our latest tests indicate that we are seeing 0x000a on register config100 to config107 (inclusive).
    These 8 registers report errors for each of the 8 JESD lanes – the two error bits are described in the data sheet as:
    bit3 = write_error : Asserted if write request and FIFO is full
    bit1 = read_error : Asserted if read request with empty FIFO

    We don't understand what the FIFOs are, where they are or how we are trying to write to a full FIFO or read from an empty FIFO - some more information regarding these registers would be much appreciated.

    Also we are driving the RESETB line high at 3V3 - this is in fielded product so not easy to correct but it would useful to know whether this issue, in itself, could be causing corruption of the DAC outputs? Also, if we are able to drive the RESETB line low perpetually, does that hold the registers in a reset state?

    Regards,

    Renan

  • Hello Renan,

    The Serdes input is running in 10bit format with 8B/10B encoded JESD204B standard. The JESD204 block would convert the encoded 10bit code into 8bit code through 8B/10B decoding. Since there is an incoming SerDes rate difference of 10/8 ratio, there need to be a FIFO between the received SerDes input and the JESD204 block. 

    If there are FIFO issues, I recommend the customer to check if there is a Serdes rate mismatch from the FPGA to the DAC, or if somehow the reference clocks to the FPGA serdes block and the DAC serdes block have misalignment.

    RESETB has internal pull-up to VDDIO18 rail, and the VDDIO18 rail has internal ESD diode connections to the other analog power rails. If powering the RESETB line at 3.3V for long period of time, the voltage may leak into VDDIO18 and to other analog rails through ESD diode. I do not think the DAC will fail immediately, but there is definitely a life time concern for the units in the field. Designer designs the ESD diodes to be quite strong for brief period of high stress, but there will be an eventual break point under constant stress of higher voltages.