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LM98640QML-SP: LM98640QML-SP ADC CLPIN configuration in Sample and Hold Mode

Saranraj Rajasekar
Prodigy 50 points
Part Number: LM98640QML-SP

Dear Sir/Madam,

   I am using LM98640QML ADC for one of my projects for data acquisition. Here My Video signal Voltage is 1.5 to 4.8V(Black level is 1.4V) we are scaling down to this signal to 0 to 2V by using op AMP .

So our ADC will receive 0 to 2V input signal on OS1+ pin(Non inverting). I am using Sample and Hold mode for data acquiring. Inn datasheet they have given 

 In Sample/Hold Mode, the DC bias point of the input pin is typically set by actuating the input clamp switch  during optical black pixels which connects the input pins to the VCLP pin DC voltage. The signal controlling this switch is CLPIN. CLPIN is an external signal connected on the CLPIN pin.

Taking the average of these signal components will result in a final “clamped” DC bias point that is close to the Black Level signal voltage. To provide a more precise DC bias point (i.e. a voltage closer to the Black Level voltage), the CLPIN pulse can be “gated” by the internally generated CLAMP clock.

But In datasheet then have mentioned CLPIN for CDS mode in fig17 & 18.

So what will be the CLPIN function in S/H mode . PFA of my circuit. 

It well be very useful for me and  application if anyone explained deeply on this topic.

I have connected My i/p signal to OS+ pin and vclp to OS-. .  CLPIN pin kept it as open.

My question is to set a bias point , do i need to connect any ref voltage level on CLPIN pin or Can it be generated by BIT register configuration ? 

VCLP pin to be connected to OS- I/P ? 

Thanks in Advance

  • 0
    TI__Mastermind 49176 points

    Hello Saranraj,

    Can you please tell about the image sensor, is it a CCD sensor or CMOS sensor? As outlined in the datasheet for S/H mode, the reference level signal must be connected to OS+ pin and the video level signal must be connected to the OS- pin. The output code will be the difference between OS+ and OS- i.e., the difference between the reference level and video level. OS- must never be taken higher than OS+. Taking OS- higher than OS+ will result in a 0 output.

    Regarding CLPIN, the CLPIN signal is used to control the operation of the Input Clamping operation that sets the DC operating point of the OS- pin periodically. When used with CCD line scanning sensors (as is typical for the LM98640) this clamping is normally done at the beginning of the line during the dummy or optical black pixels. When CLPIN Gating Enable is true, then the internal Input Clamp switch is closed when CLPIN and the internal Clamp signal are both true. When CLPIN Gating Enable is false, the Input Clamp switch is closed the entire time that the CLPIN signal is high. Since the operation of the Input Clamp switch can distort the converted value of pixels it is best to only operate the switch when the pixel values are unimportant to the application (i.e., during dummy pixels).

  • 0 in reply to Praveen Aroul
    TI__Mastermind 49176 points

    Hello Saranraj,

    I will close the post since I haven't heard back from you. If you have any pending questions, feel free to post them here.