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ADS1118: Interfacing ads1118

Ajay kumar
Prodigy 20 points
Part Number: ADS1118

Hi,

Greeting of the day!!

I am interfacing ads1118 with fgpa board( xc7a100t),with spi 3 wire mode(cs' permanently tied to gnd) and configuring registers with its default value .I am trying to read adc channel 0 with input given as 2.5v, but i am reading -1.DOUT pin is always high ,i have attached din ,sclk cro results. i have few questions

1.do i want to configure DOUT/DRDY' as interrupt pin at controller side?

2.what is minimum clock speed required for the device to work ?

3.Is 3 wire spi mode applicable to the device?

 

With regards

Ajay

  • 0
    TI__Mastermind 43041 points

    Hi Ajay,

    SCLK should idle low, not high, as shown in your scope shot. This is mentioned in section 9.5.3 in the ADS1118 datasheet. Please fix this issue before doing anything else.

    You should be monitoring the DOUT/DRDY pin to see when DRDY transitions from high to low. When your controller detects this, you must follow the datasheet protocols for retrieving data (section 9.5.7).

    I am not sure what the minimum SCLK speed is, this is not defined in the datasheet. What SCLK do you want to run the ADC at?

    According to section 9.5.1, the ADS1118 can operate in 3-wire SPI mode.

    -Bryan

  • 0 in reply to Bryan Lizon86
    Prodigy 20 points

    Hi Bryan,

    I am trying write to register to operate ADC in continuous mode operation and   clock pulses are coming only once .there is also drop in sclk ,I am configuring for 8mhz ,but i am getting 500khz.The DOUT/DRDY pin is not changing ( stay high since board reset).Shall we conclude the device(ADS1118) is gone.

    With Regards

    Ajay kumar

  • 0 in reply to Ajay kumar
    TI__Mastermind 43041 points

    Hi Ajay,

    The ADS1118 datasheet states that the minimum SCLK period is 250 ns, which is 4 MHz. The clock is running too fast, please slow it down.

    -Bryan

  • 0 in reply to Bryan Lizon86
    Prodigy 20 points

    Hi Bryan,

    I have made the Sclk to 4MHz (Since my IDE is allowing that much only ),I am not able to write to the register,DOUT is still high state .The clock get reduced to 250KHz(i am configuring 4MHz),can you propose  a solution.

    With Regards

    Ajay

  • 0 in reply to Ajay kumar
    TI__Mastermind 43041 points

    Hi Ajay,

    I am not sure why your controller is reducing the SCLK frequency, but this is not an ADC issue.

    The ADS1118 clocks out data on the falling edge of SCLK. This was correct in the last logic analyzer plot you sent. However, this most recent logic analyzer plot shows data clocking out on the rising edge. Please correct this issue in order for the ADS1118 to provide data properly,

    I would suggest reading the interface and data retrieval section of the datasheet (9.5) very carefully in order to fully understand how the ADS1118 operates. Many of these issues you are experiencing are explained in detail in that document.

    -Bryan