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TSW14J57EVM: TSW40RF82EVM LMFSHD = 82121, 4x Interpolation ”CONFIGURE DAC” Button

user1120926
Prodigy 110 points
Part Number: TSW14J57EVM
Other Parts Discussed in Thread: LMK04828, DAC38RF82, ADC32RF45, DAC38RF82EVM, TSW40RF80EVM, LMX2582

Combination of　TSW14J57EVM　and TSW40RF82EVM.

User's Guide SLAU706A-January2017-Revised September2017.

made the following settings by referring to the quick start procedure in Section 4,
It is not output from the DAC. Is the procedure wrong?

TSW40RF82EVM LMFSHD = 82121, 4x Interpolation

DAC Clock Frequency (MHz): 8487.36
#of DACs: Dual DACs
#of IQ pairs per: real input
#of serdes lanes per DAC: 4Lanes
Desired: 4x

on-chip PLL-PLL Enable: V
M: 6
N: 1
Ref Freq (MHz): 368.64

LOG window: Currrent Serdes Lane Rate 11059.20MHz
HSDCPRO ini file: DAC38RF8x_LMF_821

The following procedure has been changed.
・ Next to press the LOAD DEFAULT button
I pressed the CONFIGURE DAC button.
If you do not press the LOAD DEFAULT button
No signal was output from the DAC.

Next, the following operation procedure was performed.
5 Optionl Modes nad Infomation →
5.1.2 DAC NCO Adjustment →
5.2 DAC Pattern Generation
I changed the following files.
Load: DAC38RF8x_LMF_841_RevD.ini →
DAC38RF8x_LMF_821_RevD.ini
Change Data Rage (SPS) to 491.52M → 221.84M
Set the Tone Selection to: Complex → Real

Verify: Verify:
-LED D2 on the TSW14J56 falshes → off

  • 0
    TI__Mastermind 24150 points

    Hi,

    I have just followed the user's guide and was able to replicate the procedure up to the end of section 4 without any issues so I can confirm that the procedure is correct.

    Can you confirm that you can successfully generate a DAC tone by following section 4 without changes? I guess I am having a hard time knowing when you are seeing problems -  Is this during section 4 or is the problem only showing after you modify the settings as mentioned? (changing to real tone in LMF_821 mode)

    Thanks, Chase

  • 0 in reply to Chase W
    Prodigy 110 points

    Thank you for your reply.

    You can use Section 4 without modification to verify that you can successfully generate a DAC tone.

    I tried 2 patterns, but no signal was output.
    (1) The settings were changed after items 4 and 5.
    (2) The power was turned off and then on again, and the setting was changed in the middle of item 4.

  • 0 in reply to user1120926
    TI__Mastermind 24150 points

    Hi,

    Can you send screen captures of the TSW40RF8x GUI and also the HSDC Pro window please.

    What is the current limit set to on the 12V power supply for the TSW14J57EVM?

    If you check the constant input box (1), then adjust the NCO frequency (2), then press the Update NCO button (3), do you see the tone on a spectrum analyzer at the NCO frequency?

    Thanks

  • 0 in reply to Chase W
    TI__Mastermind 24150 points

    For the TSW40RF8x GUI, please send me images of these six pages:

    • DAC38RF8x → Quick Start
    • DAC38RF8x → DAC38RF8x → Clocking
    • DAC38RF8x → DAC38RF8x → Digital (DAC A)
    • LMK04828 → PLL1 Configuration
    • LMK04828 → PLL2 Configuration
    • LMK04828 → Clock Outputs

    Thanks

  • 0 in reply to Chase W
    Prodigy 110 points

    Thank you for your reply.

    TSW14J57EVM 12V power supply.  current limit  3A.

     DAC Clock Frequency (MHz): 8487.36
    #of DACs: Dual DACs
    #of IQ pairs per: real input
    #of serdes lanes per DAC: 4Lanes
    Desired: 4x

    CONFIGURE DAC button.

    Check the steady-status input box (1), adjust the NCO frequency (2), and press the update NCO button (3) to display the tone of the spectrum analyzer of the NCO frequency.

  • 0 in reply to Chase W
    Prodigy 110 points

    Next, the following operation procedure was performed.
    5 Optionl Modes nad Infomation →
    5.1.2 DAC NCO Adjustment →
    5.2 DAC Pattern Generation
    I changed the following files.
    Load: DAC38RF8x_LMF_841_RevD.ini →DAC38RF8x_LMF_821_RevD.ini
    Change Data Rage (SPS) to 491.52M → 2211.84M
    Set the Tone Selection to: Complex → Real

    Verify: Verify:
    -LED D2 on the TSW14J56 falshes → off

    It is not output from the DAC.

  • 0 in reply to user1120926
    TI__Mastermind 24150 points

    A few things:

    • First, increase the current limit for the TSW14J57EVM from 3A to 4A.
    • In LMF=821, the FPGA reference clock changes from 122.88MHz to 276.48MHz.
    • To change the FPGA reference clock, on the LMK04828 → PLL1 Configuration, adjust the N divider to 1152. 

    • On the LMK04828 → Clock Outputs, adjust the DCLK divider from 11 to 8.

    Adjusting the N Divider on PLL1 changes the LMK04828 DCLK from 2949.12MHz to 2211.84MHz. This is important because if the DCLK is remains at 2949.12MHz, the FPGA clock divider would have to be 10.667 in order for the FPGA reference clock of 276.48MHz to be generated. Since all dividers must be integers, if the DCLK remains at 2949.12MHz, then the divider is rounded up to 11 which makes the FPGA reference clock as 268.1MHz which is incorrect.

    Please let me know if this resolves your issue.

    Thanks, Chase

  • 0 in reply to Chase W
    Prodigy 110 points

    Thanks for the answer.

    TSW14J57EVM Current Limit 4A

    PLL1 Configuration, adjust the N divider to 1152. 

    Clock Outputs, adjust the DCLK divider from 11 to 8.

    It is not output from the DAC.

    Verify: LED D2 on the TSW14J57 OFF.

  • 0 in reply to user1120926
    TI__Mastermind 24150 points

    Please allow me a few days to test this in our lab and see what other modifications are needed to function. 

  • 0 in reply to Chase W
    Prodigy 110 points

    Thank you very much for your help.

  • 0 in reply to user1120926
    TI__Mastermind 24150 points

    Hi, I am having trouble in getting the LMF821 mode to work in any configuration currently and I'm beginning to wonder if there is a bug on the capture card side. I just wanted to let you know that I am actively working on this and will provide an update to you as I discover the root cause of these issues. I would suggest to continue evaluation in the LMF841 mode for the meantime. My apologies for this experience.

  • 0 in reply to Chase W
    Prodigy 110 points

    OK.
    Thank you in advance for your hard work.


    Can you tell me the actual value of the maximum speed of SerDes Lane Rate of TSW14J57EVM and TSW40RF82EVM regardless of the mode?

  • 0 in reply to user1120926
    TI__Mastermind 24150 points

    The max SerDes for the TSW14J57 is 15 Gbps, the max SerDes for the DAC38RF82 is 12.8 Gbps, and the max SerDes for the ADC32RF45 is 12.5 Gbps,

  • 0 in reply to Chase W
    Prodigy 110 points

    Have you tried the above values on this board?

  • 0 in reply to user1120926
    TI__Mastermind 24150 points

    Hi, yes these lane rates are verified using the ADC and DAC specific EVM. I personally have not checked the max serdes rates on this TSW40RF82EVM board, however it will be the same. I will try to have a solution ready for you by early next week. Thank you for being patient .

    Regards

  • 0 in reply to Chase W
    TI__Mastermind 24150 points

    Hi,

    We have been able to generate tones using HSDC Pro with the DAC38RF82EVM without issues. The reason there is an issue when trying to configure for this mode using the TSW40RF80EVM is because of the way the clocking is connected in hardware on the EVM. The previously suggested solutions will not work because of a limitation on the VCO0(2370MHz-2630MHz) and VCO1 (2920MHz-3080MHz) of the LMK04828 part. This means that we are unable to use the LMK04828 alone to generate the necessary clock via the PLL2.

    You should however be able to use the onboard LMX2582 to synthesize the required clock. This LMX2582 is connected to the LMK04828 CLKin1 input. In this case, go under the ADC tab and choose settings to match the following image.

    This should set the LMX2582 to generate an 1105.92MHz signal (which will become the new DCLKoutX). Then make the following changes on the LMK04828 tabs as below:

  • 0 in reply to Chase W
    Prodigy 110 points 
    Thank you for your reply.
I understand the theory, but I can't change it.
Could you give me a CFG file?
  • 0 in reply to user1120926
    TI__Mastermind 24150 points

    Hi, you should be able to modify the tab. Try to power off and power back on the TSW40RF80EVM maybe. Attached is a configuration file for the LMX2582 settings. Thanks

    4428.LMX_1105p92M.cfg

  • 0 in reply to Chase W
    Prodigy 110 points

    Hello

    You can change the tabs,

    Even if I changed it as instructed,

    it didn't work, so I asked for a CFG file.

    Thank you for the CFG file.

    I have tried it, but there are two problems.

    ・one

    TSW40RF8x EVM GUI-> DAC38RF8x-> DAC38RF8x-> Digital tag

    Sampling 8487.36MHZ

    NCO = 1960M

    Constant Input enabled

    At the time of setting The output of the DAC is not 1960M,

    It will be 2295MHz. Is it an error in the PLL settings?

    ・Two

     LED D2 now flashes when DAC38RF8x_LMF_821 is set on HSDC.

    It seems that synchronization has been established,

    but The set waveform is not output.

     

    The problem will be difficult, so Not only LMX2582 in CFG file,

    Please also set LMK04828 and DAC38RF82.

    Would you please give me a configuration file that combines everything into one?

  • 0 in reply to user1120926
    TI__Mastermind 24150 points

    Hi, It seems there is a problem when saving the configuration using the TSW40RF80EVM GUI so what I have done is set up an DAC38RF82EVM in our lab using and then combined the saved configuration from the DAC38RF82EVM with the LMX2582 configuration from the TSTW40RF80EVM GUI.

    I am glad to hear that the LED D2 is flashing now, this confirms the LMX2582 is functioning correctly and the FPGA reference is correctly divided. When you load this configuration, can you verify whether or not the DAC PLL is locking. Check that the PLL LF Voltage reads as 3, 4, or 5. If not, please verify that the DAC CLK divider is set to 3. Then try to trigger the JESD Core reset and trigger SYSREF button. Before doing this, I would power cycle both the TSW14J57 and the TSW40RF80 boards as well as close out of the softwares.

    Thanks

  • 0 in reply to Chase W
    Prodigy 110 points

    Hello
    Why not try with TSW40RF82EVM?

    I tried TSW40RF82_LMF821_config.cfg,
    It became the following state.

    one
    SW40RF8x EVM GUI> DAC38RF8x-> DAC38RF8x-> Digital Tag
    Sampling 8487.36MHZ
    NCO = 1960M
    Constant input valid
    When set, the DAC output is not 1960M,
    It will be 2300MHz.
    The noise floor will be zigzag.

    two
    Does not blink when LED D2 is set to HSDC and DAC38RF8x_LMF_821.
    The set waveform is not output.

    TSW40RF82_LMF821_config.cfg
    It's LMX2582, but isn't it 0x0C21 instead of 0x24 0x0C11?

    Also, it seems that there is a stroke order for the devices.
    Is there a rule to set LMX2582 next to LMK04828?

    Send the CFG file in the following state.
    one
    SW40RF8x EVM GUI> DAC38RF8x-> DAC38RF8x-> Digital Tag
    Sampling 8487.36MHZ
    NCO = 1960M
    Constant input valid
    When set, the DAC output is not 1960M,
    It will be 1980M.
    The noise floor will be zigzag.

    two
    LED D2 now flashes when DAC38RF8x_LMF_821 is set to HSDC.
    It seems that synchronization has been established,
    However, the set waveform is not output.

    Make sure the PLL LF voltage is 7.
    In addition, the PLL was confirmed to be unlocked at (adress = 0x05) of DAC38RF82.
    I have verified that the DAC CLK divider is set to 3.
    Next, I tried to trigger the JESD core reset and trigger SYSREF button. It did not recover.
    Before doing this, I power cycled both the TSW14J57 board and the TSW40RF80 board and closed the software.

  • 0 in reply to user1120926
    TI__Mastermind 24150 points

    Hi, I had to use the DAC38RF82EVM to first once again verify the configuration was function as well as use the GUI to save the configuration for you because was unable to save the configuration using the TSW40RF80 GUI due to software problem (the save button would not save the configuration). I have been able to get this working today with HSDC Pro by using the attached LMX2582 configuration. The difference is this configuration re-calibrates the LMX2582 PLL at the end of setting its registers.

    Here are the steps I have used to get this working again today. Let's first verify you are able to have this working before attempting to combine the configuration files into a single configuration which I can help with after:

    1. Power off the TSW40RF82EVM and close out of software.
    2. Power cycle the EVM and open the software (Run as administrator if available).
    3. Choose DAC38RF82 for Device.
    4. Press LOAD DEFAULT.
    5. Change interpolation to 4x
    6. Press CONFIGURE DAC
    7. Switch to LMK04828->PLL1 Configuration tab
    8. Enable the CLKin1 Bipolar buffer
    9. Disable the CLKin0 Bipolar buffer
    10. Change CLKin1 Out Mux to Fin
    11. Ensure OSCout Source is set to OSCin
    12. Switch to LMK04828->PLL2 Configuration tab
    13. Change VCO Mux to External VCO
    14. Switch to LMK04828->Clock Outputs tab
    15. Change FPGA divider to  4
    16. Change DAC Clock divider to 3
    17. Uncheck Output Drive Level for DAC Clock
    18. Uncheck Input  Drive Level for DAC Clock
    19. Switch  to Low Level View tab
    20. Load the attached LMX2582 configuration (LMX_1105p92M_new.cfg)
    21. Switch to DAC38RF8x->Quick Start tab
    22. Choose PLL Auto Tune
    23. Switch to DAC38RF8x->DAC38RF8x->Clocking tab
    24. Press Check Clock Alarms button ,  the two lights on the bottom will turn off indicating the DAC PLL is locked.
    25. Press Check Loop Filter Voltage, the PLL LF Voltage should read 3, 4, or 5. (If not, try to PLL Auto Tune again)
    26. Switch to DAC38RF8x->DAC38RF8x->Digital DAC A
    27. Uncheck Constant Input
    28. Change NCO Frequency(MHz) to desired value. (Image below shows NCO set  to 1500 MHz)
    29. Press UPDATE NCO
    30. In HSDC Pro, choose 2.21184GSPS data rate and enter tone at desired frequency (Image below shows real tone set at 500MHz)
    31. Switch to DAC38RF8x->Quick Start tab
    32. Press Reset DAC JESD Core & SYSREF TRIGGER
    33. Tone should appear on spectrum analyzer

    The below image shows NCO = 1500MHz and 250.12MHz tone on TSW40RF82EVM.

    Regards

  • 0 in reply to Chase W
    Prodigy 110 points

    Thank you!!
    I was able to do the same.

    However, even if I save the CFG file from the TSW40RF8xEVM GUI,
    It didn't work.

    Next, at the beginning and end of LMX2582 of the saved data
    I added calibration 0x00 0x221C, but it didn't work.

    Next, save LMX2582 of the data
    When I replaced it with the data in LMX_1105p92M_new.cfg,
    It worked.
    I didn't know where the problem was.

    I will send you the configuration file that can be combined into one setting.
    After loading the data, you need to press the Reset DAC JESD Core & SYSREF TRIGER button.

  • 0 in reply to user1120926
    TI__Mastermind 24150 points

    Excellent. I am glad it is working for you and that you were able to combine to a single configuration file. I just loaded your latest configuration onto my board and can verify function as well.

    Now, as to why it did not work before, I have compared the LMX2582 configuration registers between the two files and I have found that in the TSW40RF82_LMF821_config_user1120926_20220325.cfg configuration file, all of the undocumented registers (according to the LMX2582 datasheet) are being written to with value 0x0000. I imagine these registers must remain at default values and not be overwritten with 0x0000 for this device to function. In the LMX_1105p92M_new.cfg configuration file I sent before, these undocumented registers are not written to.

    Regards, Chase

  • 0 in reply to Chase W
    Prodigy 110 points

    Hi,
    Why did you set the following settings to Uncheck?
    17.Uncheck Output Drive Level for DAC Clock
    18.Uncheck Input Drive Level for DAC Clock

    The default setting is check.

  • +1 in reply to user1120926
    TI__Mastermind 24150 points

    This was just a troubleshooting step that remained from the previous debugging - I suggested these bits as off while we were first getting the PLLs to set on your hardware and also to eliminate any possibility of these features to be the problem.

    Now that it works, you should enable these bits to lower the noise floor of the divided DAC clock.

  • 0 in reply to Chase W
    Prodigy 110 points

    Thank you for your support for a long time.
    Please correct the problem of LMX2582 of TSW40RF8x EVM GUI.