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ADS62P25: Input Clock verification

Tensil Sebastian
Prodigy 170 points
Part Number: ADS62P25

Hello Together,

I am using ADS62P25IRGCT in my design, The input clock I am providing is to ADC is by converting single-ended signal to the differential.

 The input is from FPGA,1.8V LVCMOS ,125MHz signal. I am configuring the ADC output as LVDS.

The circuit and simulation result is attached below.

Could you please review and let me know whether the clock side circuit is ok or not

Thanks in advance,

Tensil Sebastian

Clock circuit simulationSimulation resultHIgh speed ADC circuit.pdf

  • 0
    TI__Mastermind 20755 points

    Hi Tensil,

    I would reduce the 6dB pad that you currently have to 3dB or less. The ADS62P25 supports 3.3Vpp LVCMOS so there is no need to attenuate the clock input by 6dB.

    Thanks, Chase

  • 0 in reply to Chase W
    Prodigy 170 points

    Hello Chase,

    Thanks for the quick response.

    So, I just want to know with the current circuit will the ADC work without any issue. Whether the input clock differential output voltage levels are ok?. In the datasheet, it is  mentioned as +/-0.35Vpp

    If the output is configured as LVDS can we give the input clock as LVCMOS.

    Also, If we are giving the Input clock as LVCMOS, Whether the CLKOUTP,CLKOUTM will be LVDS or LVCMOS

    If I am providing LVCMOS input for the clock, the ADC supported is 3.3Vpp LVCMOS level. But my FPGA is driving 1.8V output, So will this be a problem if I connect the FPGA output directly to the ADC.

    And also if I am connecting FPGA output directly to the ADC, to which pin do I need to connect, CLKP (25) or CLKM (26). If I need to connect to CLKP what I need to do with the CLKM.Do I need to connect CLKM to GND or floating?

    Thanks,

    Tensil Sebastian

  • +1 in reply to Tensil Sebastian
    TI__Mastermind 20755 points

    Hi Tensil, my apologies for being unclear in my previous message, I read LVCMOS and immediately referred to the 3.3Vpp level rather than the LVDS level in the datasheet despite your design showing differential clock input. These differential levels will likely work without any issues, however for proper LVDS driven input, you should modify the design to have a differential swing by ±350mV as the datasheet mentions. 

    See my comments in blue below:

    So, I just want to know with the current circuit will the ADC work without any issue. Whether the input clock differential output voltage levels are ok?. In the datasheet, it is  mentioned as +/-0.35Vpp No, you will have to reduce to ±350mV swing or change to single ended clock input.

    If the output is configured as LVDS can we give the input clock as LVCMOS. Yes, any clock method works with this part regardless of the output format. The output is set by address 0x14 if using serial programming interface and is set by the SEN input when using the parallel interface.

    Also, If we are giving the Input clock as LVCMOS, Whether the CLKOUTP,CLKOUTM will be LVDS or LVCMOS The clock buffer output should be LVDS format since it is set with the output data format.

    If I am providing LVCMOS input for the clock, the ADC supported is 3.3Vpp LVCMOS level. But my FPGA is driving 1.8V output, So will this be a problem if I connect the FPGA output directly to the ADC. 1.8V would be enough to meet the "sine-wave" 1.5Vpp requirement if you AC-couple the signal.

    And also if I am connecting FPGA output directly to the ADC, to which pin do I need to connect, CLKP (25) or CLKM (26). If I need to connect to CLKP what I need to do with the CLKM. Do I need to connect CLKM to GND or floating? Connect the SE clock to CLKP. The CLKM input will be connected to GND. See below design recommendation from our datasheet (on page 50).

  • 0 in reply to Chase W
    Prodigy 170 points

    Hello Chase,

    Thank you so much for the explanations.

    I have modified the circuit.

    Could you please confirm the amplitudes are ok now.

    Thanks in advance,

    Tensil Sebastian

  • +1 in reply to Tensil Sebastian
    TI__Mastermind 20755 points

    Hi Tensil,

    When I mentioned ±350mV swing, this is referring to the DIFF line shown in your simulation so your amplitude is still high by a factor of near 2. You want the maximum value to be around +350mV and the minimum value to be around -350mV for the DIFF measurement. (peak to peak voltage of 700mV)

    Hope this helps. Regards, Chase