ADS4449: signal inquiry

Chong Yu

Intellectual 1435 points

Part Number: ADS4449

Hi team,

My customer need assistance.

Parts:ADS4449IZCR.

Vivadio software

After AD sampling, it enters FPGA and captures data through FPGA,

There are many burrs in the time domain, and the noise bottom is unstable and the stray signal is large in the frequency domain.

I'd like to ask under what circumstances such spikes will be caused and how to reduce spurious signals

Please help. Thanks.

over 2 years ago

0 Rob Reeder over 2 years ago

TI__Mastermind 27420 points

Hi Chong,

Can you please send us a copy of the customer's schematic?

Regards,

Rob

0 Luke Chiang over 2 years ago in reply to Rob Reeder

Prodigy 230 points

Sorry, it's not convenient for us to provide schematic diagram. Can't you give some suggestions only from the information provided now? Or can you tell me that these conditions are normal? I mean, is it really possible for this chip to behave like this in some harsh environment?

0 Luke Chiang over 2 years ago in reply to Rob Reeder

Prodigy 230 points

This is the RF input circuit diagram, output and various control directly connected to FPGA

0 Luke Chiang over 2 years ago in reply to Luke Chiang

Prodigy 230 points

It is the clock.

0 Rob Reeder over 2 years ago in reply to Luke Chiang

TI__Mastermind 27420 points

Hi Chong,

Here could be a number of reasons the ADC or the data could be displayed like this. Its difficult to tell what is going on with your circuit. I full schematic would be better for us to have and look over to check.

Is the data on the output, in the pictures above with an analog input signal applied to the ADC? Or you are just clocking the ADC and looking at the outputs in the time domain?

Regards,

Rob

0 jim s over 2 years ago in reply to Rob Reeder

TI__Guru* 91947 points

Chong,

I would suggest sending a ramp test pattern from all channels using registers 0x25, 0x2B, 0x31 and 0x37 to verify proper timing of the digital interface between the ADC and FPGA. Once a valid ramp is observed by all four channels, you can start testing the analog front end data.

Regards,

Data converters

Data converters forum

ADS4449: signal inquiry