ADS5500-EP: Data outputs problem.

Hi Ahmet,

Can you please share a better schematic diagram picture or upload the schematic file?

Try AC coupling the amplifier and ADC, meaning put 0.1uF capacitors in series with outputs of the amplifier.

Its possible the output common mode voltage is not in line with the input common mode voltage of the ADC.

Regards,

Rob

Hi Rob,

When I changed the Internal DLL, the problem was fixed.

But after a while he has the same problem again.

I have attached the circuit diagram and oscilloscope images of the voltages applied to its analog inputs.

Best regards.

Ahmet

7140.ADC_Files.rar

Hi Ahmet,

The internal DLL should be off when sampling at 25MSPS.

Would it be possible to share the amplifier part number in the schematic above? I can't make out the number.

Also, can you please also measure the DC voltage on the analog inputs? Both and P and N inputs should be +1.55V.

Regards,

Rob

Hi Rob,

The amplifier part code is AD8132ARMZ.

Both P and N input voltages are 1.55 volts relative to GND.

We apply a differential voltage both the P and N inputs. (min:1.15volt, max:2.95volt relative to GND) 

I shared the oscilloscope outputs in my previous reply.

CLKP and CLKM inputs are provided differentially by FPGA. The pulse amplitude is 3.3 volts. Will this pose a problem?

Regards,

Ahmet

Hi Ahmet,

I think it might be best to send a few output plots from the ADC in either time domain or frequency domain, FFT.

I would be best to show with and without an input signal applied.

If you can forward a better picture of your schematic above that might help too. The picture supplied previously is to fuzzy to make out the details of the circuit.

Regards,

Rob

Hi Rob,

I have shared the pictures below. 

I have also attached the circuit schematic as a pdf file.

Regards,

Ahmet

Input signals (CLKP, CLKM);

Output Signals (CLKOUT , D0);

Schematic pdf file; 0207.ADC.pdf

Hi Rob,

I noticed that,

When the Output Enable pin is activated, I get good results from the data outputs for a short time (about 50-100 microseconds) but the result is bad when activated for a long time.

I have attached a picture regarding it.

Sampling rate = 25 MSPS

Regards,

Hi Ahmet,

This is very odd. It would be best if you send us your entire schematic, so we can see what these signals are connected to? Is the CLKOUT connected to multiple devices?

Thanks,

Rob

Hi Rob,

CLKOUT and other data outputs are connected directly and only to the FPGA.

Regards,

Ahmet